linux-kernel - Re: [PATCH v2 4/4] arm: dts: visconti: Add DT support for Toshiba Visconti5 ethernet controller

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Date:   Fri, 12 Feb 2021 10:32:09 +0100
From:   Arnd Bergmann <arnd@...nel.org>
To:     Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
Cc:     "David S . Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Giuseppe Cavallaro <peppe.cavallaro@...com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        Jose Abreu <joabreu@...opsys.com>,
        DTML <devicetree@...r.kernel.org>,
        Networking <netdev@...r.kernel.org>,
        punit1.agrawal@...hiba.co.jp, yuji2.ishikawa@...hiba.co.jp,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 4/4] arm: dts: visconti: Add DT support for Toshiba
 Visconti5 ethernet controller

On Fri, Feb 12, 2021 at 4:03 AM Nobuhiro Iwamatsu
<nobuhiro1.iwamatsu@...hiba.co.jp> wrote:
> @@ -384,6 +398,16 @@ spi6: spi@...46000 {
>                         #size-cells = <0>;
>                         status = "disabled";
>                 };
> +
> +               piether: ethernet@...00000 {
> +                       compatible = "toshiba,visconti-dwmac";

Shouldn't there be a more specific compatible string here, as well as the
particular version of the dwmac you use?

In the binding example, you list the device as "dma-coherent",
but in this instance, it is not marked that way. Can you find out
whether the device is in fact connected properly to a cache-coherent
bus?

Note that failing to mark it as cache-coherent will make the device
rather slow and possibly not work correctly if it is in fact coherent,
but the default is non-coherent since a lot of SoCs are lacking
that hardware support.

       Arnd