linux-kernel - Re: [PATCH] coresight: etm4x: Add ETM PIDs for Cortex-A55 and Cortex-A78

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Message-ID: <a0f2a95c4e4d3d079cf8379bd49b527a@codeaurora.org>
Date:   Sat, 13 Feb 2021 16:48:50 +0530
From:   Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
To:     Mike Leach <mike.leach@...aro.org>
Cc:     Mathieu Poirier <mathieu.poirier@...aro.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Leo Yan <leo.yan@...aro.org>,
        Coresight ML <coresight@...ts.linaro.org>,
        Stephen Boyd <swboyd@...omium.org>,
        Denis Nikitin <denik@...omium.org>,
        linux-arm-msm@...r.kernel.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] coresight: etm4x: Add ETM PIDs for Cortex-A55 and
 Cortex-A78

Hi Mike,

On 2021-02-13 16:24, Mike Leach wrote:
> Hi Sai,
> 
> This patch does not apply to coresight/next - possibly because the PID
> for A55 has been added in an earlier patch ( [b8336ad947e19 ]
> coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75).
> 

Apologies, my remote was still pointing to linaro coresight repo,
https://git.linaro.org/kernel/coresight.git, I have now updated
the remote to a proper kernel.org coresight repo and will post
the updated patchset.

Thanks,
Sai

> 
> 
> 
> On Fri, 12 Feb 2021 at 17:23, Sai Prakash Ranjan
> <saiprakash.ranjan@...eaurora.org> wrote:
>> 
>> Add ETM PIDs for Cortex-A55 and Cortex-A78 to the list of
>> supported ETMs.
>> 
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
>> ---
>>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++
>>  1 file changed, 2 insertions(+)
>> 
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c 
>> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index b20b6ff17cf6..193233792ab5 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -1713,7 +1713,9 @@ static const struct amba_id etm4_ids[] = {
>>         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
>>         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
>>         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
>> +       CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
>>         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
>> +       CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
>>         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
>>         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
>>         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 
>> Cortex-A55 */
>> 
>> base-commit: 1efbcec2ef8c037f1e801c76e4b9434ee2400be7
>> --
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
>> member
>> of Code Aurora Forum, hosted by The Linux Foundation
>> 
> 
> 
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation