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Message-Id: <20210215231943.36910-4-adrien.grassein@gmail.com>
Date: Tue, 16 Feb 2021 00:19:38 +0100
From: Adrien Grassein <adrien.grassein@...il.com>
To: unlisted-recipients:; (no To-header on input)
Cc: robh+dt@...nel.org, shawnguo@...nel.org, s.hauer@...gutronix.de,
kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
catalin.marinas@....com, will@...nel.org, krzk@...nel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Adrien Grassein <adrien.grassein@...il.com>
Subject: [PATCH 3/8] arm64: dts: imx8mm-nitrogen-r2: add espi2 support
Add the description for espi support.
Signed-off-by: Adrien Grassein <adrien.grassein@...il.com>
---
.../boot/dts/freescale/imx8mm-nitrogen-r2.dts | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
index 1b29d8a12d04..22acde0f3ba8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
@@ -10,6 +10,14 @@ / {
model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";
+ clocks {
+ clk16m: clk16m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ };
+ };
+
reg_wlan_vmmc: regulator-wlan-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -39,6 +47,19 @@ &A53_3 {
cpu-supply = <®_buck3>;
};
+/* J15 */
+&ecspi2 {
+ assigned-clocks = <&clk IMX8MM_CLK_ECSPI2>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
+ assigned-clock-rates = <40000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
@@ -270,6 +291,15 @@ &iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
--
2.25.1
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