linux-kernel - Re: DMA-buf and uncached system memory

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <cc98293f-eb4f-bf0c-2e25-7e41b12d5ca2@amd.com>
Date:   Mon, 15 Feb 2021 13:25:01 +0100
From:   Christian König <christian.koenig@....com>
To:     Lucas Stach <l.stach@...gutronix.de>,
        Simon Ser <contact@...rsion.fr>
Cc:     linaro-mm-sig@...ts.linaro.org,
        "Sharma, Shashank" <Shashank.Sharma@....com>,
        lkml <linux-kernel@...r.kernel.org>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        linux-media <linux-media@...r.kernel.org>
Subject: Re: DMA-buf and uncached system memory

Am 15.02.21 um 13:16 schrieb Lucas Stach:
> [SNIP]
>>>> Userspace components can then of course tell the exporter what the
>>>> importer needs, but validation if that stuff is correct and doesn't
>>>> crash the system must happen in the kernel.
>>> What exactly do you mean by "scanout requires non-coherent memory"?
>>> Does the scanout requestor always set the no-snoop PCI flag, so you get
>>> garbage if some writes to memory are still stuck in the caches, or is
>>> it some other requirement?
>> Snooping the CPU caches introduces some extra latency, so what can
>> happen is that the response to the PCIe read comes to late for the
>> scanout. The result is an underflow and flickering whenever something is
>> in the cache which needs to be flushed first.
> Okay, that confirms my theory on why this is needed. So things don't
> totally explode if you don't do it, but to in order to guarantee access
> latency you need to take the no-snoop path, which means your device
> effectively gets dma-noncoherent.

Exactly. My big question at the moment is if this is something AMD 
specific or do we have the same issue on other devices as well?

>> On the other hand when the don't snoop the CPU caches we at least get
>> garbage/stale data on the screen. That wouldn't be that worse, but the
>> big problem is that we have also seen machine check exceptions when
>> don't snoop and the cache is dirty.
> If you attach to the dma-buf with a struct device which is non-coherent
> it's the exporters job to flush any dirty caches. Unfortunately the DRM
> caching of the dma-buf attachments in the DRM framework will get a bit
> in the way here, so a DRM specific flush might be be needed. :/ Maybe
> moving the whole buffer to uncached sysmem location on first attach of
> a non-coherent importer would be enough?

Could work in theory, but problem is that for this to do I have to tear 
down all CPU mappings and attachments of other devices.

Apart from the problem that we don't have the infrastructure for that we 
don't know at import time that a buffer might be used for scan out. I 
would need to re-import it during fb creation or something like this.

Our current concept for AMD GPUs is rather that we try to use uncached 
memory as much as possible. So for the specific use case just checking 
if the exporter is AMDGPU and has the flag set should be enough for not.

>> So this should better be coherent or you can crash the box. ARM seems to
>> be really susceptible for this, x86 is fortunately much more graceful
>> and I'm not sure about other architectures.
> ARM really dislikes pagetable setups with different attributes pointing
> to the same physical page, however you should be fine as long as all
> cached aliases are properly flushed from the cache before access via a
> different alias.

Yeah, can totally confirm that and had to learn it the hard way.

Regards,
Christian.

>
> Regards,
> Lucas
>