linux-kernel - Re: [PATCH v5 2/9] cxl/mem: Find device capabilities

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Message-ID: <20210217122253.00007bc2@Huawei.com>
Date:   Wed, 17 Feb 2021 12:22:53 +0000
From:   Jonathan Cameron <Jonathan.Cameron@...wei.com>
To:     Ben Widawsky <ben.widawsky@...el.com>
CC:     <linux-cxl@...r.kernel.org>, <linux-acpi@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-nvdimm@...ts.01.org>,
        <linux-pci@...r.kernel.org>, Bjorn Helgaas <helgaas@...nel.org>,
        "Chris Browy" <cbrowy@...ry-design.com>,
        Christoph Hellwig <hch@...radead.org>,
        "Dan Williams" <dan.j.williams@...el.com>,
        David Hildenbrand <david@...hat.com>,
        David Rientjes <rientjes@...gle.com>,
        Ira Weiny <ira.weiny@...el.com>,
        "Jon Masters" <jcm@...masters.org>,
        Rafael Wysocki <rafael.j.wysocki@...el.com>,
        Randy Dunlap <rdunlap@...radead.org>,
        Vishal Verma <vishal.l.verma@...el.com>,
        "John Groves (jgroves)" <jgroves@...ron.com>,
        "Kelley, Sean V" <sean.v.kelley@...el.com>,
        Colin Ian King <colin.king@...onical.com>,
        Dan Carpenter <dan.carpenter@...cle.com>
Subject: Re: [PATCH v5 2/9] cxl/mem: Find device capabilities

On Tue, 16 Feb 2021 20:09:51 -0800
Ben Widawsky <ben.widawsky@...el.com> wrote:

> Provide enough functionality to utilize the mailbox of a memory device.
> The mailbox is used to interact with the firmware running on the memory
> device. The flow is proven with one implemented command, "identify".
> Because the class code has already told the driver this is a memory
> device and the identify command is mandatory.
> 
> CXL devices contain an array of capabilities that describe the
> interactions software can have with the device or firmware running on
> the device. A CXL compliant device must implement the device status and
> the mailbox capability. Additionally, a CXL compliant memory device must
> implement the memory device capability. Each of the capabilities can
> [will] provide an offset within the MMIO region for interacting with the
> CXL device.
> 
> The capabilities tell the driver how to find and map the register space
> for CXL Memory Devices. The registers are required to utilize the CXL
> spec defined mailbox interface. The spec outlines two mailboxes, primary
> and secondary. The secondary mailbox is earmarked for system firmware,
> and not handled in this driver.
> 
> Primary mailboxes are capable of generating an interrupt when submitting
> a background command. That implementation is saved for a later time.
> 
> Reported-by: Colin Ian King <colin.king@...onical.com> (coverity)
> Reported-by: Dan Carpenter <dan.carpenter@...cle.com> (smatch)
> Link: https://www.computeexpresslink.org/download-the-specification
> Signed-off-by: Ben Widawsky <ben.widawsky@...el.com>
> Reviewed-by: Dan Williams <dan.j.williams@...el.com> (v2)

Looks good to me. 

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>