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Message-Id: <20210219143028.207975-8-adrien.grassein@gmail.com>
Date: Fri, 19 Feb 2021 15:30:26 +0100
From: Adrien Grassein <adrien.grassein@...il.com>
To: unlisted-recipients:; (no To-header on input)
Cc: krzk@...nel.org, robh+dt@...nel.org, shawnguo@...nel.org,
s.hauer@...gutronix.de, kernel@...gutronix.de, festevam@...il.com,
linux-imx@....com, catalin.marinas@....com, will@...nel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Adrien Grassein <adrien.grassein@...il.com>
Subject: [PATCH v3 7/9] arm64: dts: imx8mm-nitrogen-r2: add FlexSPI
Add FlexSPI description an pin muxing.
Signed-off-by: Adrien Grassein <adrien.grassein@...il.com>
Reviewed-by: Krzysztof Kozlowski <krzk@...nel.org>
---
.../boot/dts/freescale/imx8mm-nitrogen-r2.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
index 9a210ca63731..0fd8e2a54073 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
@@ -78,6 +78,12 @@ ethphy0: ethernet-phy@4 {
};
};
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi>;
+ status = "okay";
+};
+
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -367,6 +373,17 @@ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x159
>;
};
+ pinctrl_flexspi: flexspigrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+ >;
+ };
+
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09
--
2.25.1
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