linux-kernel - [RFC 17/19] arm64: dts: imx8mq: Add interconnect properties to icc consumer nodes

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Message-Id: <1613750416-11901-18-git-send-email-abel.vesa@nxp.com>
Date:   Fri, 19 Feb 2021 18:00:14 +0200
From:   Abel Vesa <abel.vesa@....com>
To:     Rob Herring <robh@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <kernel@...gutronix.de>,
        Lucas Stach <l.stach@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Georgi Djakov <djakov@...nel.org>,
        Dong Aisheng <aisheng.dong@....com>,
        Peng Fan <peng.fan@....com>,
        Martin Kepplinger <martink@...teo.de>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Cc:     NXP Linux Team <linux-imx@....com>, Abel Vesa <abel.vesa@....com>
Subject: [RFC 17/19] arm64: dts: imx8mq: Add interconnect properties to icc consumer nodes

We add all the properties necessary to control the interconnect
based on the required rates all the way from consumers to the dram.
The fsl,icc-rate specifies the minimum required rate the consumer needs
in order to operate.
For now, only the fec, usdhc1 and usdhc2 are added as consumers.

Signed-off-by: Abel Vesa <abel.vesa@....com>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a64b4bf31f5..43760316052f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1112,6 +1112,9 @@ usdhc1: mmc@...40000 {
 				             "fsl,imx7d-usdhc";
 				reg = <0x30b40000 0x10000>;
 				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&icc IMX8MQ_ICM_USDHC1 &icc IMX8MQ_ICS_DRAM>;
+				interconnect-names = "path";
+				fsl,icc-rate = <266666>;
 				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
@@ -1127,6 +1130,9 @@ usdhc2: mmc@...50000 {
 				             "fsl,imx7d-usdhc";
 				reg = <0x30b50000 0x10000>;
 				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&icc IMX8MQ_ICM_USDHC2 &icc IMX8MQ_ICS_DRAM>;
+				interconnect-names = "path";
+				fsl,icc-rate = <266666>;
 				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
@@ -1169,6 +1175,9 @@ fec1: ethernet@...e0000 {
 				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&icc IMX8MQ_ICM_ENET &icc IMX8MQ_ICS_DRAM>;
+				interconnect-names = "path";
+				fsl,icc-rate = <800000>;
 				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
 				         <&clk IMX8MQ_CLK_ENET_TIMER>,
-- 
2.29.2