[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20210222114030.26445-4-kishon@ti.com>
Date: Mon, 22 Feb 2021 17:10:29 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: Kishon Vijay Abraham I <kishon@...com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Tom Joseph <tjoseph@...ence.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>
CC: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH v3 3/4] dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index d06f0c4464c6..aed437dac363 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -16,12 +16,14 @@ allOf:
properties:
compatible:
oneOf:
- - description: PCIe EP controller in J7200
+ - const: ti,j721e-pcie-ep
+ - description: PCIe EP controller in AM64
items:
- - const: ti,j7200-pcie-ep
+ - const: ti,am64-pcie-ep
- const: ti,j721e-pcie-ep
- - description: PCIe EP controller in J721E
+ - description: PCIe EP controller in J7200
items:
+ - const: ti,j7200-pcie-ep
- const: ti,j721e-pcie-ep
reg:
@@ -66,7 +68,6 @@ required:
- power-domains
- clocks
- clock-names
- - dma-coherent
- max-functions
- phys
- phy-names
--
2.17.1
Powered by blists - more mailing lists