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Message-Id: <20210223061830.1913700-1-daniel@0x0f.com>
Date: Tue, 23 Feb 2021 15:18:22 +0900
From: Daniel Palmer <daniel@...f.com>
To: devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
soc@...nel.org, sboyd@...nel.org
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
w@....eu, Daniel Palmer <daniel@...f.com>
Subject: [PATCH 0/8] ARM: mstar: cpupll
This series adds a scrappy driver for the PLL that generates
the cpu clock on MStar/SigmaStar ARMv7 SoCs.
Unfortunately there isn't much documentation for this thing
so there are few magic values and guesses.
This needs to come after the MPLL DT changes.
Daniel Palmer (8):
dt-bindings: clk: mstar msc313 cpupll binding description
clk: mstar: msc313 cpupll clk driver
ARM: mstar: Add cpupll to base dtsi
ARM: mstar: Link cpupll to cpu
ARM: mstar: Link cpupll to second core
ARM: mstar: Add OPP table for infinity
ARM: mstar: Add OPP table for infinity3
ARM: mstar: Add OPP table for mercury5
.../bindings/clock/mstar,msc313-cpupll.yaml | 45 ++++
arch/arm/boot/dts/mstar-infinity.dtsi | 34 +++
arch/arm/boot/dts/mstar-infinity2m.dtsi | 2 +
arch/arm/boot/dts/mstar-infinity3.dtsi | 58 +++++
arch/arm/boot/dts/mstar-mercury5.dtsi | 36 +++
arch/arm/boot/dts/mstar-v7.dtsi | 9 +
drivers/clk/mstar/Kconfig | 7 +
drivers/clk/mstar/Makefile | 1 +
drivers/clk/mstar/clk-msc313-cpupll.c | 228 ++++++++++++++++++
9 files changed, 420 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml
create mode 100644 drivers/clk/mstar/clk-msc313-cpupll.c
--
2.30.0.rc2
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