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Date:   Tue, 23 Feb 2021 02:10:24 +0200
From:   Vladimir Oltean <>
To:     Florian Fainelli <>
Cc:, Andrew Lunn <>,
        Vivien Didelot <>,
        "David S. Miller" <>,
        Jakub Kicinski <>,
        Russell King <>,
        open list <>
Subject: Re: [PATCH net v2 2/2] net: dsa: b53: Support setting learning on

On Mon, Feb 22, 2021 at 03:44:21PM -0800, Florian Fainelli wrote:
> > In sf2, CORE_DIS_LEARN is at address 0xf0, while in b53, B53_DIS_LEARN
> > is at 0x3c. Are they even configuring the same thing?
> They are the SF2 switch was integrated with a bridge that would flatten
> its address space such that there would be no need to access the
> registers indirectly like what b53_srab does.
> This is the reason why we have the SF2_PAGE_REG_MKADDR() macro to
> convert from a {page, offset} tuple to a memory mapped address and here
> 0x3c << 2 = 0xf0.

Thanks, now I have more context to understand why sf2 uses one kind of
I/O and b53 another, and also how the paged address map managed by the
b53 driver gets linearized before accessing the sf2 registers.

Reviewed-by: Vladimir Oltean <>

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