linux-kernel - Re: [PATCH v21 05/26] x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6e644e1d-7034-20f1-4850-336b143ba01c@intel.com>
Date:   Wed, 24 Feb 2021 07:42:05 -0800
From:   "Yu, Yu-cheng" <yu-cheng.yu@...el.com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     x86@...nel.org, "H. Peter Anvin" <hpa@...or.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
        linux-doc@...r.kernel.org, linux-mm@...ck.org,
        linux-arch@...r.kernel.org, linux-api@...r.kernel.org,
        Arnd Bergmann <arnd@...db.de>,
        Andy Lutomirski <luto@...nel.org>,
        Balbir Singh <bsingharora@...il.com>,
        Cyrill Gorcunov <gorcunov@...il.com>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Eugene Syromiatnikov <esyr@...hat.com>,
        Florian Weimer <fweimer@...hat.com>,
        "H.J. Lu" <hjl.tools@...il.com>, Jann Horn <jannh@...gle.com>,
        Jonathan Corbet <corbet@....net>,
        Kees Cook <keescook@...omium.org>,
        Mike Kravetz <mike.kravetz@...cle.com>,
        Nadav Amit <nadav.amit@...il.com>,
        Oleg Nesterov <oleg@...hat.com>, Pavel Machek <pavel@....cz>,
        Peter Zijlstra <peterz@...radead.org>,
        Randy Dunlap <rdunlap@...radead.org>,
        "Ravi V. Shankar" <ravi.v.shankar@...el.com>,
        Vedvyas Shanbhogue <vedvyas.shanbhogue@...el.com>,
        Dave Martin <Dave.Martin@....com>,
        Weijiang Yang <weijiang.yang@...el.com>,
        Pengfei Xu <pengfei.xu@...el.com>,
        Haitao Huang <haitao.huang@...el.com>
Subject: Re: [PATCH v21 05/26] x86/fpu/xstate: Introduce CET MSR and XSAVES
 supervisor states

On 2/24/2021 7:34 AM, Borislav Petkov wrote:
> On Wed, Feb 17, 2021 at 02:27:09PM -0800, Yu-cheng Yu wrote:
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index 546d6ecf0a35..fae6b3ea1f6d 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -933,4 +933,23 @@
>>   #define MSR_VM_IGNNE                    0xc0010115
>>   #define MSR_VM_HSAVE_PA                 0xc0010117
>>   
>> +/* Control-flow Enforcement Technology MSRs */
>> +#define MSR_IA32_U_CET		0x6a0 /* user mode cet setting */
>> +#define MSR_IA32_S_CET		0x6a2 /* kernel mode cet setting */
>> +#define CET_SHSTK_EN		BIT_ULL(0)
>> +#define CET_WRSS_EN		BIT_ULL(1)
>> +#define CET_ENDBR_EN		BIT_ULL(2)
>> +#define CET_LEG_IW_EN		BIT_ULL(3)
>> +#define CET_NO_TRACK_EN		BIT_ULL(4)
>> +#define CET_SUPPRESS_DISABLE	BIT_ULL(5)
>> +#define CET_RESERVED		(BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
>> +#define CET_SUPPRESS		BIT_ULL(10)
>> +#define CET_WAIT_ENDBR		BIT_ULL(11)
>> +
>> +#define MSR_IA32_PL0_SSP	0x6a4 /* kernel shadow stack pointer */
>> +#define MSR_IA32_PL1_SSP	0x6a5 /* ring-1 shadow stack pointer */
>> +#define MSR_IA32_PL2_SSP	0x6a6 /* ring-2 shadow stack pointer */
>> +#define MSR_IA32_PL3_SSP	0x6a7 /* user shadow stack pointer */
>> +#define MSR_IA32_INT_SSP_TAB	0x6a8 /* exception shadow stack table */
> 
> When you look at the formatting in that file and the MSR numbers in it, what
> stops you from formatting your addition the same way?
> 

Ah, got it.  I will add some leading zeros.  Thanks!

--
Yu-cheng