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Message-ID: <CAFqH_50_SKgwgtV+8UX+4v=S9mY9tf0HCQaCKgGCQzWuBfQ7ug@mail.gmail.com>
Date: Thu, 25 Feb 2021 17:26:36 +0100
From: Enric Balletbo Serra <eballetbo@...il.com>
To: Hsin-Yi Wang <hsinyi@...omium.org>
Cc: Matthias Brugger <matthias.bgg@...il.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
Enric Balletbo i Serra <enric.balletbo@...labora.com>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] arm64: dts: mediatek: Add gce client reg for display subcomponents
Hi Hsin-Yi,
Thank you for the patch.
Missatge de Hsin-Yi Wang <hsinyi@...omium.org> del dia dl., 1 de febr.
2021 a les 12:05:
>
> Add mediatek,gce-client-reg for ccorr, aal, gamma, dither.
>
> Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
> Signed-off-by: Hsin-Yi Wang <hsinyi@...omium.org>
FWIW this removes some errors from the boot log like this:
platform 14010000.aal: error -2 can't parse gce-client-reg property (0)
Tested-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index b3b8afec5ab9a..0ed37dd9d80b4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1058,6 +1058,7 @@ ccorr0: ccorr@...0f000 {
> interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> };
>
> aal0: aal@...10000 {
> @@ -1067,6 +1068,7 @@ aal0: aal@...10000 {
> interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> };
>
> gamma0: gamma@...11000 {
> @@ -1075,6 +1077,7 @@ gamma0: gamma@...11000 {
> interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> };
>
> dither0: dither@...12000 {
> @@ -1083,6 +1086,7 @@ dither0: dither@...12000 {
> interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> };
>
> dsi0: dsi@...14000 {
> --
> 2.30.0.365.g02bc693789-goog
>
>
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