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Date:   Thu, 25 Feb 2021 11:10:02 +0800
From:   peng.fan@....nxp.com
To:     sboyd@...nel.org, robh+dt@...nel.org, shawnguo@...nel.org,
        s.hauer@...gutronix.de
Cc:     kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
        ulf.hansson@...aro.org, adrian.hunter@...el.com,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mmc@...r.kernel.org, Peng Fan <peng.fan@....com>
Subject: [PATCH V3 3/5] arm64: dts: imx8qxp: correct usdhc clock-names sequence

From: Peng Fan <peng.fan@....com>

Per dt-bindings, the clock-names sequence should be ipg ahb per to pass
dtbs_check.

Signed-off-by: Peng Fan <peng.fan@....com>
---
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e46faac1fe71..1d522de7b017 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -366,9 +366,9 @@ usdhc1: mmc@...10000 {
 			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x5b010000 0x10000>;
 			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
-			clock-names = "ipg", "per", "ahb";
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>,
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>;
+			clock-names = "ipg", "ahb", "per";
 			power-domains = <&pd IMX_SC_R_SDHC_0>;
 			status = "disabled";
 		};
@@ -378,9 +378,9 @@ usdhc2: mmc@...20000 {
 			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x5b020000 0x10000>;
 			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
-			clock-names = "ipg", "per", "ahb";
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>,
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>;
+			clock-names = "ipg", "ahb", "per";
 			power-domains = <&pd IMX_SC_R_SDHC_1>;
 			fsl,tuning-start-tap = <20>;
 			fsl,tuning-step= <2>;
@@ -392,9 +392,9 @@ usdhc3: mmc@...30000 {
 			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x5b030000 0x10000>;
 			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
-				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
-			clock-names = "ipg", "per", "ahb";
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>,
+				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>;
+			clock-names = "ipg", "ahb", "per";
 			power-domains = <&pd IMX_SC_R_SDHC_2>;
 			status = "disabled";
 		};
-- 
2.30.0

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