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Message-Id: <20210226200414.167762-12-konrad.dybcio@somainline.org>
Date: Fri, 26 Feb 2021 21:03:41 +0100
From: Konrad Dybcio <konrad.dybcio@...ainline.org>
To: phone-devel@...r.kernel.org
Cc: ~postmarketos/upstreaming@...ts.sr.ht, martin.botka@...ainline.org,
angelogioacchino.delregno@...ainline.org,
marijn.suijten@...ainline.org,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Amit Kucheria <amitk@...nel.org>,
Zhang Rui <rui.zhang@...el.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH 11/41] arm64: dts: qcom: sdm630: Add interconnect and opp table to sdhc_1
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
The SDHC port 1 has interconnects and can make use of DVFS:
define the interconnections and the OPP table in order to
optimize performance and power consumption.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@...ainline.org>
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index c85a4a71fb0c..ed7d22aa734c 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1106,14 +1106,42 @@ sdhc_1: sdhci@...4000 {
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "core", "iface", "xo", "ice";
+ interconnects = <&a2noc 2 &a2noc 10>,
+ <&gnoc 0 &cnoc 27>;
+ interconnect-names = "sdhc1-ddr", "cpu-sdhc1";
+ operating-points-v2 = <&sdhc1_opp_table>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
+ power-domains = <&rpmpd SDM660_VDDCX>;
bus-width = <8>;
non-removable;
status = "disabled";
+
+ sdhc1_opp_table: sdhc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <200000 140000>;
+ opp-avg-kBps = <130718 133320>;
+ };
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ opp-peak-kBps = <250000 160000>;
+ opp-avg-kBps = <196078 150000>;
+ };
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <4096000 4096000>;
+ opp-avg-kBps = <1338562 1338562>;
+ };
+ };
};
mmcc: clock-controller@...0000 {
--
2.30.1
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