lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sat, 27 Feb 2021 19:26:02 +0530
From:   Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
To:     Stephen Boyd <swboyd@...omium.org>
Cc:     devicetree@...r.kernel.org, Rajendra Nayak <rnayak@...eaurora.org>,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Andy Gross <agross@...nel.org>,
        Sibi Sankar <sibis@...eaurora.org>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 8/9] arm64: dts: qcom: sc7280: Add AOSS QMP node

On 2021-02-27 00:16, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
>> On 2021-02-26 01:11, Stephen Boyd wrote:
>> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
>> >> Add a DT node for the AOSS QMP on SC7280 SoC.
>> >>
>> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
>> >> ---
>> >>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++
>> >>  1 file changed, 14 insertions(+)
>> >>
>> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >> index 65c1e0f2fb56..cbd567ccc04e 100644
>> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >> @@ -9,6 +9,7 @@
>> >>  #include <dt-bindings/clock/qcom,rpmh.h>
>> >>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>> >>  #include <dt-bindings/mailbox/qcom-ipcc.h>
>> >> +#include <dt-bindings/power/qcom-aoss-qmp.h>
>> >>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> >>
>> >>  / {
>> >> @@ -368,6 +369,19 @@ pdc: interrupt-controller@...0000 {
>> >>                         interrupt-controller;
>> >>                 };
>> >>
>> >> +               aoss_qmp: qmp@...0000 {
>> >
>> > power-domain-controller@...0000? power-controller@...0000?
>> >
>> 
>> Its an AOSS message RAM and all other SM* SoCs have as qmp@
>> and the dt binding as well, I see only SM8150 with power-controller,
>> that should probably be fixed?
> 
> Node name should be generic while still being meaningful. Nobody knows
> what qmp is, but power-controller makes sense. Can you fix this and the
> others to be power-controller?
> 

Ok makes sense, I will post changing others as well and see if we get
any comments there.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ