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Message-ID: <CAAhSdy0ZJF2uGzYDGxuhbR831GJtyRorfjAMbU8CtJ=0twiZig@mail.gmail.com>
Date:   Sat, 27 Feb 2021 09:25:57 +0530
From:   Anup Patel <anup@...infault.org>
To:     Palmer Dabbelt <palmerdabbelt@...gle.com>
Cc:     Anup Patel <Anup.Patel@....com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Atish Patra <Atish.Patra@....com>,
        Alistair Francis <Alistair.Francis@....com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] RISC-V: Enable CPU Hotplug in defconfigs

Hi Palmer,

On Fri, Feb 19, 2021 at 12:45 PM Palmer Dabbelt
<palmerdabbelt@...gle.com> wrote:
>
> On Mon, 08 Feb 2021 21:46:20 PST (-0800), Anup Patel wrote:
> > The CPU hotplug support has been tested on QEMU, Spike, and SiFive
> > Unleashed so let's enable it by default in RV32 and RV64 defconfigs.
> >
> > Signed-off-by: Anup Patel <anup.patel@....com>
> > ---
> >  arch/riscv/configs/defconfig      | 1 +
> >  arch/riscv/configs/rv32_defconfig | 1 +
> >  2 files changed, 2 insertions(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index 8c3d1e451703..6c0625aa96c7 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -17,6 +17,7 @@ CONFIG_BPF_SYSCALL=y
> >  CONFIG_SOC_SIFIVE=y
> >  CONFIG_SOC_VIRT=y
> >  CONFIG_SMP=y
> > +CONFIG_HOTPLUG_CPU=y
> >  CONFIG_JUMP_LABEL=y
> >  CONFIG_MODULES=y
> >  CONFIG_MODULE_UNLOAD=y
> > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> > index 2c2cda6cc1c5..8dd02b842fef 100644
> > --- a/arch/riscv/configs/rv32_defconfig
> > +++ b/arch/riscv/configs/rv32_defconfig
> > @@ -18,6 +18,7 @@ CONFIG_SOC_SIFIVE=y
> >  CONFIG_SOC_VIRT=y
> >  CONFIG_ARCH_RV32I=y
> >  CONFIG_SMP=y
> > +CONFIG_HOTPLUG_CPU=y
> >  CONFIG_JUMP_LABEL=y
> >  CONFIG_MODULES=y
> >  CONFIG_MODULE_UNLOAD=y
>
> Thanks, this is on for-next.

This patch was missed in your PR for Linux-5.12-rc1

Regards,
Anup

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