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Message-ID: <CACRpkdYM3x6pJU3Vi+EEHtC3wD1DkrtVbGDd3PFHWL0fxjSA9g@mail.gmail.com>
Date: Wed, 3 Mar 2021 16:31:41 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: David Laight <David.Laight@...lab.com>
Cc: Will Deacon <will@...nel.org>, Jian Cai <jiancai@...gle.com>,
Nick Desaulniers <ndesaulniers@...gle.com>,
Manoj Gupta <manojgupta@...gle.com>,
Luis Lozano <llozano@...gle.com>,
clang-built-linux <clang-built-linux@...glegroups.com>,
Nathan Chancellor <nathan@...nel.org>,
Russell King <linux@...linux.org.uk>,
Catalin Marinas <catalin.marinas@....com>,
James Morris <jmorris@...ei.org>,
"Serge E. Hallyn" <serge@...lyn.com>,
Arnd Bergmann <arnd@...db.de>,
Masahiro Yamada <masahiroy@...nel.org>,
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Andreas Färber <afaerber@...e.de>,
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<linux-security-module@...r.kernel.org>
Subject: Re: [PATCH v4] ARM: Implement SLS mitigation
On Wed, Mar 3, 2021 at 4:29 PM David Laight <David.Laight@...lab.com> wrote:
> > On Tue, Feb 23, 2021 at 11:05 AM Will Deacon <will@...nel.org> wrote:
> > I wrote some suggestions on follow-ups in my reply, and I can
> > help out doing some of the patches, I think.
> >
> > Since ARM32 RET is mov pc, <>
> > git grep 'mov.*pc,' | wc -l gives 93 sites in arch/arm.
> > I suppose these need to come out:
> >
> > mov pc, lr
> > dsb(nsh);
> > isb();
>
> Won't that go horribly wrong for conditional returns?
It will so I would not insert it after those. It has to be
on a case-by-base basis, I am not planning any
search and replace operations.
Yours,
Linus Walleij
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