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Message-ID: <a2526aef-ed2e-c33b-0afb-b5363fb17969@ti.com>
Date: Thu, 4 Mar 2021 14:14:25 +0530
From: Lokesh Vutla <lokeshvutla@...com>
To: Grygorii Strashko <grygorii.strashko@...com>,
Nishanth Menon <nm@...com>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
Vignesh Raghavendra <vigneshr@...com>
CC: <linux-kernel@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
Kishon Vijay Abraham I <kishon@...com>,
Tero Kristo <kristo@...nel.org>
Subject: Re: [PATCH 1/4] arm64: dts: ti: am64-main: Add CPSW DT node
On 04/03/21 12:51 am, Grygorii Strashko wrote:
> From: Vignesh Raghavendra <vigneshr@...com>
>
> Add CPSW3g DT node with two external ports, MDIO and CPTS support. For
> CPSW3g DMA channels the ASEL is set to 15 (AM642x per DMA channel coherency
> feature), so that CPSW DMA channel participates in Coherency and thus avoid
> need to cache maintenance for SKBs. This improves bidirectional TCP
> performance by up to 100Mbps (on 1G link).
>
> Signed-off-by: Vignesh Raghavendra <vigneshr@...com>
> Signed-off-by: Grygorii Strashko <grygorii.strashko@...com>
nit pick. In $subject : k3-am64-main.
Thanks and regards,
Lokesh
> ---
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 74 ++++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 +
> 2 files changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> index 5f85950daef7..80443dbf272c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> @@ -178,6 +178,12 @@
> compatible = "ti,am654-chipid";
> reg = <0x00000014 0x4>;
> };
> +
> + phy_gmii_sel: phy@...4 {
> + compatible = "ti,am654-phy-gmii-sel";
> + reg = <0x4044 0x8>;
> + #phy-cells = <1>;
> + };
> };
>
> main_uart0: serial@...0000 {
> @@ -402,4 +408,72 @@
> ti,otap-del-sel-ddr50 = <0x9>;
> ti,clkbuf-sel = <0x7>;
> };
> +
> + cpsw3g: ethernet@...0000 {
> + compatible = "ti,am642-cpsw-nuss";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x8000000 0x0 0x200000>;
> + reg-names = "cpsw_nuss";
> + ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
> + clocks = <&k3_clks 13 0>;
> + assigned-clocks = <&k3_clks 13 1>;
> + assigned-clock-parents = <&k3_clks 13 9>;
> + clock-names = "fck";
> + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
> +
> + dmas = <&main_pktdma 0xC500 15>,
> + <&main_pktdma 0xC501 15>,
> + <&main_pktdma 0xC502 15>,
> + <&main_pktdma 0xC503 15>,
> + <&main_pktdma 0xC504 15>,
> + <&main_pktdma 0xC505 15>,
> + <&main_pktdma 0xC506 15>,
> + <&main_pktdma 0xC507 15>,
> + <&main_pktdma 0x4500 15>;
> + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
> + "tx7", "rx";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpsw_port1: port@1 {
> + reg = <1>;
> + ti,mac-only;
> + label = "port1";
> + phys = <&phy_gmii_sel 1>;
> + mac-address = [00 00 de ad be ef];
> + };
> +
> + cpsw_port2: port@2 {
> + reg = <2>;
> + ti,mac-only;
> + label = "port2";
> + phys = <&phy_gmii_sel 2>;
> + mac-address = [00 01 de ad be ef];
> + };
> + };
> +
> + cpsw3g_mdio: mdio@f00 {
> + compatible = "ti,cpsw-mdio","ti,davinci_mdio";
> + reg = <0x0 0xf00 0x0 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&k3_clks 13 0>;
> + clock-names = "fck";
> + bus_freq = <1000000>;
> + };
> +
> + cpts@...00 {
> + compatible = "ti,j721e-cpts";
> + reg = <0x0 0x3d000 0x0 0x400>;
> + clocks = <&k3_clks 13 1>;
> + clock-names = "cpts";
> + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "cpts";
> + ti,cpts-ext-ts-inputs = <4>;
> + ti,cpts-periodic-outputs = <2>;
> + };
> + };
> };
> diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> index 0ae8c844c482..de6805b0c72c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> @@ -28,6 +28,8 @@
> serial6 = &main_uart4;
> serial7 = &main_uart5;
> serial8 = &main_uart6;
> + ethernet0 = &cpsw_port1;
> + ethernet1 = &cpsw_port2;
> };
>
> chosen { };
>
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