linux-kernel - Re: [PATCH 1/3] clocksource/drivers/timer-ti-dm: Fix posted mode status check order

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Message-ID: <YEHjf6dcTByVvwBX@atomide.com>
Date:   Fri, 5 Mar 2021 09:53:35 +0200
From:   Tony Lindgren <tony@...mide.com>
To:     Grygorii Strashko <grygorii.strashko@...com>
Cc:     Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Keerthy <j-keerthy@...com>, linux-kernel@...r.kernel.org,
        linux-omap@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/3] clocksource/drivers/timer-ti-dm: Fix posted mode
 status check order

* Grygorii Strashko <grygorii.strashko@...com> [210304 20:58]:
> On 04/03/2021 09:21, Tony Lindgren wrote:
> > When the timer is configured in posted mode, we need to check the write-
> > posted status register (TWPS) before writing to the register.
...

> > --- a/drivers/clocksource/timer-ti-dm-systimer.c
> > +++ b/drivers/clocksource/timer-ti-dm-systimer.c
> > @@ -449,13 +449,13 @@ static int dmtimer_set_next_event(unsigned long cycles,
> >   	struct dmtimer_systimer *t = &clkevt->t;
> >   	void __iomem *pend = t->base + t->pend;
> > -	writel_relaxed(0xffffffff - cycles, t->base + t->counter);
> >   	while (readl_relaxed(pend) & WP_TCRR)
> >   		cpu_relax();
> > +	writel_relaxed(0xffffffff - cycles, t->base + t->counter);
> > -	writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
> >   	while (readl_relaxed(pend) & WP_TCLR)
> >   		cpu_relax();
> > +	writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
> 
> It seems static [and inline] helper here could be better solution. no?

Well we wanted to get rid of the confusing macros. And in this case I
suspect we can eventually do just one read of the pending register for
the registers used mask rather than check the status separately multiple
times. But that needs to be carefully tested and is not a fix :)

Regards,

Tony