linux-kernel - Re: [PATCH v1 3/7] PCI: New Primary to Sideband (P2SB) bridge support library

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Message-ID: <YEZ4IitUa+I9HM5F@smile.fi.intel.com>
Date:   Mon, 8 Mar 2021 21:16:50 +0200
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Bjorn Helgaas <helgaas@...nel.org>
Cc:     Wolfram Sang <wsa+renesas@...g-engineering.com>,
        Jean Delvare <jdelvare@...e.de>,
        Lee Jones <lee.jones@...aro.org>,
        Tan Jui Nee <jui.nee.tan@...el.com>,
        Jim Quinlan <james.quinlan@...adcom.com>,
        Jonathan Yong <jonathan.yong@...el.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
        linux-pci@...r.kernel.org, Jean Delvare <jdelvare@...e.com>,
        Peter Tyser <ptyser@...-inc.com>, hdegoede@...hat.com,
        henning.schild@...mens.com
Subject: Re: [PATCH v1 3/7] PCI: New Primary to Sideband (P2SB) bridge
 support library

On Mon, Mar 08, 2021 at 12:52:12PM -0600, Bjorn Helgaas wrote:
> On Mon, Mar 08, 2021 at 02:20:16PM +0200, Andy Shevchenko wrote:
> > From: Jonathan Yong <jonathan.yong@...el.com>
> > 
> > There is already one and at least one more user is coming which
> > requires an access to Primary to Sideband bridge (P2SB) in order to
> > get IO or MMIO bar hidden by BIOS. Create a library to access P2SB
> > for x86 devices.
> 
> Can you include a spec reference?

I'm not sure I have a public link to the spec. It's the 100 Series PCH [1].
The document number to look for is 546955 [2] and there actually a bit of
information about this.

> I'm trying to figure out why this
> belongs in drivers/pci/.  It looks very device-specific.

Because it's all about access to PCI configuration spaces of the (hidden)
devices.

[1]: https://ark.intel.com/content/www/us/en/ark/products/series/98456/intel-100-series-desktop-chipsets.html
[2]: https://medium.com/@jacksonchen_43335/bios-gpio-p2sb-70e9b829b403

...

> > +config PCI_P2SB
> > +	bool "Primary to Sideband (P2SB) bridge access support"
> > +	depends on PCI && X86
> > +	help
> > +	  The Primary to Sideband bridge is an interface to some PCI
> > +	  devices connected through it. In particular, SPI NOR
> > +	  controller in Intel Apollo Lake SoC is one of such devices.
> 
> This doesn't sound like a "bridge".  If it's a bridge, what's on the
> primary (upstream) side?  What's on the secondary side?  What
> resources are passed through the bridge, i.e., what transactions does
> it transfer from one side to the other?

It's a confusion terminology here. It's a Bridge according to the spec, but
it is *not* a PCI Bridge as you may had a first impression.

...

> > +	/* Unhide the P2SB device */
> > +	pci_bus_write_config_byte(bus, df, P2SBC_HIDE_BYTE, 0);
> > +
> > +	/* Read the first BAR of the device in question */
> > +	__pci_bus_read_base(bus, devfn, pci_bar_unknown, mem, PCI_BASE_ADDRESS_0, true);
> 
> I don't get this.  Apparently this normally hidden device is consuming
> PCI address space.  The PCI core needs to know about this.  If it
> doesn't, the PCI core may assign this space to another device.

Right, it returns all 1:s to any request so PCI core *thinks* it's plugged off
(like D3cold or so).

> > +	/* Hide the P2SB device */
> > +	pci_bus_write_config_byte(bus, df, P2SBC_HIDE_BYTE, P2SBC_HIDE_BIT);

-- 
With Best Regards,
Andy Shevchenko