linux-kernel - Re: [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor

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Date:   Mon, 8 Mar 2021 07:46:14 +0000
From:   Teresa Remmet <T.Remmet@...tec.de>
To:     "hs@...x.de" <hs@...x.de>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
CC:     "krzk@...nel.org" <krzk@...nel.org>,
        "linux-imx@....com" <linux-imx@....com>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "festevam@...il.com" <festevam@...il.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>
Subject: Re: [PATCH 2/2] arm64: imx8mp: imx8mp-phycore-som enable spi nor

Hello Heiko,

first thanks for the patch :).

Am Montag, den 08.03.2021, 07:40 +0100 schrieb Heiko Schocher:
> enable the mt25qu256aba spi nor on the imx8mp-phycore-som.
> 
> Signed-off-by: Heiko Schocher <hs@...x.de>
> ---
> 
>  .../dts/freescale/imx8mp-phycore-som.dtsi     | 27
> +++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> index 44a8c2337cee4..0284e7a5c6bba 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> @@ -65,6 +65,22 @@ ethphy1: ethernet-phy@0 {
>  	};
>  };
>  
> +&flexspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexspi0>;
> +	status = "okay";
> +
> +	flash0: mt25qu256aba@0 {

you can remove the label. As it is not used here right now.
Also rename the node name to device type like "flash" maybe.

I will try to test this soon.

Thanks,
Teresa


> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";
> +		spi-max-frequency = <80000000>;
> +		spi-tx-bus-width = <4>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
>  &i2c1 {
>  	clock-frequency = <400000>;
>  	pinctrl-names = "default";
> @@ -217,6 +233,17 @@ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		
> 0x11
>  		>;
>  	};
>  
> +	pinctrl_flexspi0: flexspi0grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		
> 0x1c2
> +			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
> +			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	
> 0x82
> +			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	
> 0x82
> +			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	
> 0x82
> +			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	
> 0x82
> +		>;
> +	};
> +
>  	pinctrl_i2c1: i2c1grp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400
> 001c3