linux-kernel - [PATCH v2 1/1] arm64: dts: imx8mm-nitrogen-r2: add ecspi2 support

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Message-Id: <20210308125518.255216-2-adrien.grassein@gmail.com>
Date:   Mon,  8 Mar 2021 13:55:18 +0100
From:   Adrien Grassein <adrien.grassein@...il.com>
To:     unlisted-recipients:; (no To-header on input)
Cc:     m.felsch@...gutronix.de, devicetree@...r.kernel.org,
        will@...nel.org, shawnguo@...nel.org, s.hauer@...gutronix.de,
        linux-kernel@...r.kernel.org, krzk@...nel.org, robh+dt@...nel.org,
        linux-imx@....com, kernel@...gutronix.de, catalin.marinas@....com,
        festevam@...il.com, linux-arm-kernel@...ts.infradead.org,
        Adrien Grassein <adrien.grassein@...il.com>
Subject: [PATCH v2 1/1] arm64: dts: imx8mm-nitrogen-r2: add ecspi2 support

Add the description for ecspi2 support.

Signed-off-by: Adrien Grassein <adrien.grassein@...il.com>
Reviewed-by: Krzysztof Kozlowski <krzk@...nel.org>
Reviewed-by: Fabio Estevam <festevam@...il.com>
---
 .../boot/dts/freescale/imx8mm-nitrogen-r2.dts | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
index 4f4cf7df5a5a..50c2ed0470da 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
@@ -52,6 +52,17 @@ &A53_3 {
 	cpu-supply = <&reg_buck3>;
 };
 
+/* J15 */
+&ecspi2 {
+	assigned-clocks = <&clk IMX8MM_CLK_ECSPI2>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
+	assigned-clock-rates = <40000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
@@ -286,6 +297,15 @@ &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x140
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x19
+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x19
+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x19
+		>;
+	};
+
 	pinctrl_fec1: fec1grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
-- 
2.25.1