lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAL_JsqJHRM59GC3FjvaGLCELemy1uspnGvTEFH6q0OdyBPVSjA@mail.gmail.com>
Date:   Mon, 8 Mar 2021 08:56:32 -0700
From:   Rob Herring <robh@...nel.org>
To:     Arnd Bergmann <arnd@...nel.org>
Cc:     Hector Martin <marcan@...can.st>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Marc Zyngier <maz@...nel.org>, Olof Johansson <olof@...om.net>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        Mark Kettenis <mark.kettenis@...all.nl>,
        Tony Lindgren <tony@...mide.com>,
        Mohamed Mediouni <mohamed.mediouni@...amail.com>,
        Stan Skowronek <stan@...ellium.com>,
        Alexander Graf <graf@...zon.com>,
        Will Deacon <will@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Mark Rutland <mark.rutland@....com>,
        Andy Shevchenko <andy.shevchenko@...il.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jonathan Corbet <corbet@....net>,
        Catalin Marinas <catalin.marinas@....com>,
        Christoph Hellwig <hch@...radead.org>,
        "David S. Miller" <davem@...emloft.net>,
        DTML <devicetree@...r.kernel.org>,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>,
        Linux Doc Mailing List <linux-doc@...r.kernel.org>,
        linux-samsung-soc <linux-samsung-soc@...r.kernel.org>,
        "open list:GENERIC INCLUDE/ASM HEADER FILES" 
        <linux-arch@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [RFT PATCH v3 12/27] of/address: Add infrastructure to declare
 MMIO as non-posted

On Fri, Mar 5, 2021 at 2:17 PM Arnd Bergmann <arnd@...nel.org> wrote:
>
> On Fri, Mar 5, 2021 at 7:18 PM Hector Martin <marcan@...can.st> wrote:
> >
> > On 06/03/2021 02.39, Rob Herring wrote:
> > >> -       return ioremap(res.start, resource_size(&res));
> > >> +       if (res.flags & IORESOURCE_MEM_NONPOSTED)
> > >> +               return ioremap_np(res.start, resource_size(&res));
> > >> +       else
> > >> +               return ioremap(res.start, resource_size(&res));
> > >
> > > This and the devm variants all scream for a ioremap_extended()
> > > function. IOW, it would be better if the ioremap flavor was a
> > > parameter. Unless we could implement that just for arm64 first, that's
> > > a lot of refactoring...
> >
> > I agree, but yeah... that's one big refactor to try to do now...
>
> FWIW, there is ioremap_prot() that Christoph introduced in 2019
> for a few architectures.  I suppose it would be nice to lift
> that out architecture specific code and completely replace the
> unusual variants, leaving only ioremap(), ioremap_prot() and
> memremap() but dropping the _nc, _cached, _wc, _wt and _np
> versions in favor of an extensible set of flags.
>
> Then again, I would not make that a prerequisite for the merge
> of the M1 support.
>
> > > What's the code path using these functions on the M1 where we need to
> > > return 'posted'? It's just downstream PCI mappings (PCI memory space),
> > > right? Those would never hit these paths because they don't have a DT
> > > node or if they do the memory space is not part of it. So can't the
> > > check just be:
> > >
> > > bool of_mmio_is_nonposted(struct device_node *np)
> > > {
> > >      return np && of_machine_is_compatible("apple,arm-platform");
> > > }
> >
> > Yes; the implementation was trying to be generic, but AIUI we don't need
> > this on M1 because the PCI mappings don't go through this codepath, and
> > nothing else needs posted mode. My first hack was something not too
> > unlike this, then I was going to get rid of apple,arm-platform and just
> > have this be a generic mechanism with the properties, but then we added
> > the optimization to not do the lookups on other platforms, and now we're
> > coming full circle... :-)
>
> I never liked the idea of having a list of platforms that need a
> special hack, please let's not go back to that.

I'm a fan of generic solutions as much as anyone, but not when there's
a single user. Yes, there could be more, but we haven't seen any yet
and Apple seems to have a knack for doing special things. I'm pretty
sure posted vs. non-posted has been a possibility with AXI buses from
the start, so it's not like this is a new thing we're going to see
frequently on new platforms.

A generic property we have to support forever because there's zero
visibility if someone uses them. At least with something platform
specific, we know if it's in use or can be removed. That's something I
just checked recently with some of the PPC irq work-arounds (spoiler:
yes, those 'old world Mac' are). I'm a bit less worried about this
aspect given we can probably assume someone will still be using M1
Macs in 20+ years.

The other situation I worry about here is another arch has implicitly
defaulted to non-posted instead of posted. It could just be non-posted
was what worked everywhere and Linux couldn't distinguish. Now someone
sees we have this new posted vs. non-posted handling and can optimize
some mappings on their platform and we have to have per arch defaults
(like 'dma-coherent' now).

Rob

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ