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Message-ID: <07d76b634a675b7559f471d419935b88e2ce36aa.camel@wdc.com>
Date: Tue, 9 Mar 2021 19:34:17 +0000
From: Atish Patra <Atish.Patra@....com>
To: "ben.dooks@...ethink.co.uk" <ben.dooks@...ethink.co.uk>,
"Lewis.Hanly@...rochip.com" <Lewis.Hanly@...rochip.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC: "Cyril.Jean@...rochip.com" <Cyril.Jean@...rochip.com>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
Alistair Francis <Alistair.Francis@....com>,
Anup Patel <Anup.Patel@....com>,
"Conor.Dooley@...rochip.com" <Conor.Dooley@...rochip.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"bjorn@...nel.org" <bjorn@...nel.org>,
"aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
"palmer@...belt.com" <palmer@...belt.com>,
"paul.walmsley@...ive.com" <paul.walmsley@...ive.com>,
"Ivan.Griffin@...rochip.com" <Ivan.Griffin@...rochip.com>,
"Daire.McNamara@...rochip.com" <Daire.McNamara@...rochip.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>
Subject: Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board
On Tue, 2021-03-09 at 13:30 +0000, Lewis.Hanly@...rochip.com wrote:
>
>
> From: Ben Dooks <ben.dooks@...ethink.co.uk>
> Sent: Tuesday, March 9, 2021 10:56 AM
> To: Atish Patra <atish.patra@....com>; linux-kernel@...r.kernel.org <
> linux-kernel@...r.kernel.org>
> Cc: Albert Ou <aou@...s.berkeley.edu>; Alistair Francis <
> alistair.francis@....com>; Anup Patel <anup.patel@....com>; Björn
> Töpel <bjorn@...nel.org>; devicetree@...r.kernel.org <
> devicetree@...r.kernel.org>; linux-riscv@...ts.infradead.org <
> linux-riscv@...ts.infradead.org>; Palmer Dabbelt
> <palmer@...belt.com>; Paul Walmsley <paul.walmsley@...ive.com>; Rob
> Herring < robh+dt@...nel.org>; Conor Dooley - M52691 <
> Conor.Dooley@...rochip.com>; Daire McNamara - X61553 <
> Daire.McNamara@...rochip.com>; Ivan Griffin - X61451 <
> Ivan.Griffin@...rochip.com>; Lewis Hanly - M34782 <
> Lewis.Hanly@...rochip.com>
> Subject: Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE
> board
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On 03/03/2021 20:02, Atish Patra wrote:
> > Add initial DTS for Microchip ICICLE board having only
> > essential devices (clocks, sdhci, ethernet, serial, etc).
> > The device tree is based on the U-Boot patch.
> >
> > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/
> >
> > Signed-off-by: Atish Patra <atish.patra@....com>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/microchip/Makefile | 2 +
> > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++
> > .../boot/dts/microchip/microchip-mpfs.dtsi | 329
> > ++++++++++++++++++
> > 4 files changed, 404 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-
> > icicle-kit.dts
> > create mode 100644 arch/riscv/boot/dts/microchip/microchip-
> > mpfs.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile
> > b/arch/riscv/boot/dts/Makefile
> > index 7ffd502e3e7b..fe996b88319e 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > subdir-y += sifive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > +subdir-y += microchip
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index 000000000000..622b12771fd3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-
> > kit.dtb
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-
> > kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-
> > kit.dts
> > new file mode 100644
> > index 000000000000..ec79944065c9
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > @@ -0,0 +1,72 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +#include "microchip-mpfs.dtsi"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ 1000000
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC Icicle Kit";
> > + compatible = "microchip,mpfs-icicle-kit";
> > +
> > + chosen {
> > + stdout-path = &serial0;
> > + };
> > +
> > + cpus {
> > + timebase-frequency = <RTCCLK_FREQ>;
> > + };
> > +
> > + memory@...00000 {
> > + device_type = "memory";
> > + reg = <0x0 0x80000000 0x0 0x40000000>;
> > + clocks = <&clkcfg 26>;
> > + };
> > +
>
> The latest Microchip releases have two memory nodes to provide the
> full 2GiB of memory space.
> > > For this release we want to leave it at 1GB, wip memory remapping
> > > with the newer releases.
>
Thanks for the clarification. For some reason, your reply did not land
in the mailing lists.
> > + soc {
> > + };
> > +};
> > +
> > +&serial0 {
> > + status = "okay";
> > +};
> > +
> > +&serial1 {
> > + status = "okay";
> > +};
> > +
> > +&serial2 {
> > + status = "okay";
> > +};
> > +
> > +&serial3 {
> > + status = "okay";
> > +};
> > +
> > +&sdcard {
> > + status = "okay";
> > +};
> > +
> > +&emac0 {
> > + phy-mode = "sgmii";
> > + phy-handle = <&phy0>;
> > + phy0: ethernet-phy@8 {
> > + reg = <8>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > +};
> > +
> > +&emac1 {
> > + status = "okay";
> > + phy-mode = "sgmii";
> > + phy-handle = <&phy1>;
> > + phy1: ethernet-phy@9 {
> > + reg = <9>;
> > + ti,fifo-depth = <0x01>;
> > + };
> > +};
>
>
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
--
Regards,
Atish
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