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Message-ID: <1615291538-9799-4-git-send-email-macpaul.lin@mediatek.com>
Date: Tue, 9 Mar 2021 20:05:37 +0800
From: Macpaul Lin <macpaul.lin@...iatek.com>
To: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Wendell Lin <Wendell.Lin@...iatek.com>,
Fabien Parent <fparent@...libre.com>,
Weiyi Lu <weiyi.lu@...iatek.com>,
Mars Cheng <mars.cheng@...iatek.com>,
Sean Wang <Sean.Wang@...iatek.com>,
Macpaul Lin <Macpaul.Lin@...iatek.com>,
Owen Chen <owen.chen@...iatek.com>,
Evan Green <evgreen@...omium.org>, <Yong.Wu@...iatek.com>,
Joerg Roedel <jroedel@...e.de>,
Shawn Guo <shawnguo@...nel.org>,
Marc Zyngier <marc.zyngier@....com>,
Ryder Lee <Ryder.Lee@...iatek.com>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>
CC: Ainge Hsu <ainge.hsu@...iatek.com>,
Eddie Hung <eddie.hung@...iatek.com>,
Mediatek WSD Upstream <wsd_upstream@...iatek.com>,
Macpaul Lin <macpaul.lin@...iatek.com>,
Macpaul Lin <macpaul@...il.com>,
CC Hwang <cc.hwang@...iatek.com>,
Loda Chou <loda.chou@...iatek.com>
Subject: [PATCH v9 3/4] arm64: dts: mediatek: add mt6765 support
From: Mars Cheng <mars.cheng@...iatek.com>
Add basic chip support for Mediatek 6765, include
uart node with correct uart clocks, pwrap device
Add clock controller nodes, include topckgen, infracfg,
apmixedsys and subsystem.
Signed-off-by: Mars Cheng <mars.cheng@...iatek.com>
Signed-off-by: Owen Chen <owen.chen@...iatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@...iatek.com>
Acked-by: Marc Zyngier <marc.zyngier@....com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++
arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 ++++++++++++++++++++
3 files changed, 287 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index deba27ab7657..176c817f9f9a 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
new file mode 100644
index 000000000000..36dddff2b7f8
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Mediatek MT6765
+ *
+ * (C) Copyright 2018. Mediatek, Inc.
+ *
+ * Mars Cheng <mars.cheng@...iatek.com>
+ */
+
+/dts-v1/;
+#include "mt6765.dtsi"
+
+/ {
+ model = "MediaTek MT6765 EVB";
+ compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@...00000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x1e800000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
new file mode 100644
index 000000000000..2662470fe607
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Mediatek MT6765
+ *
+ * (C) Copyright 2018. Mediatek, Inc.
+ *
+ * Mars Cheng <mars.cheng@...iatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt6765-clk.h>
+
+/ {
+ compatible = "mediatek,mt6765";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x001>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x002>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x003>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x101>;
+ };
+
+ cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x102>;
+ };
+
+ cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x103>;
+ };
+ };
+
+ clocks {
+ clk26m: clk26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk32k: clk32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@...0000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x2000>, /* GICH */
+ <0 0x0c420000 0 0x20000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ topckgen: syscon@...00000 {
+ compatible = "mediatek,mt6765-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@...01000 {
+ compatible = "mediatek,mt6765-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: pericfg@...03000 {
+ compatible = "mediatek,mt6765-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ };
+
+ scpsys: scpsys@...06000 {
+ compatible = "mediatek,mt6765-scpsys";
+ reg = <0 0x10006000 0 0x1000>; /* spm */
+ #power-domain-cells = <1>;
+ clocks = <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_MM_SEL>,
+ <&mmsys_config CLK_MM_SMI_COMMON>,
+ <&mmsys_config CLK_MM_SMI_COMM0>,
+ <&mmsys_config CLK_MM_SMI_COMM1>,
+ <&mmsys_config CLK_MM_SMI_LARB0>,
+ <&imgsys CLK_IMG_LARB2>,
+ <&mmsys_config CLK_MM_SMI_IMG>,
+ <&camsys CLK_CAM_LARB3>,
+ <&camsys CLK_CAM_DFP_VAD>,
+ <&camsys CLK_CAM>,
+ <&camsys CLK_CAM_CCU>,
+ <&mmsys_config CLK_MM_SMI_CAM>;
+ clock-names = "mfg", "mm",
+ "mm-0", "mm-1", "mm-2", "mm-3",
+ "isp-0", "isp-1", "cam-0", "cam-1",
+ "cam-2", "cam-3", "cam-4";
+ infracfg = <&infracfg>;
+ smi_comm = <&smi_common>;
+ };
+
+ apmixed: syscon@...0c000 {
+ compatible = "mediatek,mt6765-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@...00a80 {
+ compatible = "mediatek,mt6765-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x50>;
+ };
+
+ uart0: serial@...02000 {
+ compatible = "mediatek,mt6765-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_UART0>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@...03000 {
+ compatible = "mediatek,mt6765-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_UART1>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ audio: syscon@...20000 {
+ compatible = "mediatek,mt6765-audsys", "syscon";
+ reg = <0 0x11220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mipi_rx_ana_csi0a: syscon@...10000 {
+ compatible = "mediatek,mt6765-mipi0a",
+ "syscon";
+ reg = <0 0x11c10000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys_config: syscon@...00000 {
+ compatible = "mediatek,mt6765-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ };
+
+ smi_common: smi_common@...02000 {
+ compatible = "mediatek,mt6765-smi-common", "syscon";
+ reg = <0 0x14002000 0 0x1000>;
+ };
+
+ imgsys: syscon@...20000 {
+ compatible = "mediatek,mt6765-imgsys", "syscon";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ venc_gcon: syscon@...00000 {
+ compatible = "mediatek,mt6765-vcodecsys", "syscon";
+ reg = <0 0x17000000 0 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@...00000 {
+ compatible = "mediatek,mt6765-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ }; /* end of soc */
+};
--
2.18.0
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