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Message-ID: <4a41ecf2-2203-f3db-f728-fc0d1b0426c6@ti.com>
Date: Wed, 10 Mar 2021 23:04:30 +0530
From: Vignesh Raghavendra <vigneshr@...com>
To: Nishanth Menon <nm@...com>, Tero Kristo <kristo@...nel.org>
CC: Rob Herring <robh+dt@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Pratyush Yadav <p.yadav@...com>,
Lokesh Vutla <lokeshvutla@...com>
Subject: Re: [PATCH 1/2] arm64: dts: ti: k3-am64-main: Add OSPI node
Hi Nishanth
On 3/9/21 6:35 PM, Vignesh Raghavendra wrote:
> AM64 SoC has a single Octal SPI (OSPI) instance under Flash SubSystem
> (FSS). Add DT entry for the same.
>
> Signed-off-by: Vignesh Raghavendra <vigneshr@...com>
> ---
Please ignore the series. I see some instabilities in my testing... Will
repost once I have addressed them. Sorry for the noise.
Regards
Vignesh
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> index 5f85950daef7..bcec4fa444b5 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> @@ -402,4 +402,29 @@ sdhci1: mmc@...0000 {
> ti,otap-del-sel-ddr50 = <0x9>;
> ti,clkbuf-sel = <0x7>;
> };
> +
> + fss: bus@...0000 {
> + compatible = "simple-bus";
> + reg = <0x00 0x0fc00000 0x00 0x70000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ospi0: spi@...0000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x0fc40000 0x00 0x100>,
> + <0x05 0x00000000 0x01 0x00000000>;
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + clocks = <&k3_clks 75 6>;
> + assigned-clocks = <&k3_clks 75 6>;
> + assigned-clock-parents = <&k3_clks 75 7>;
> + assigned-clock-rates = <166666666>;
> + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
> + };
> + };
> };
>
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