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Message-ID: <20210310194644.GA1218@ranerica-svr.sc.intel.com>
Date:   Wed, 10 Mar 2021 11:46:44 -0800
From:   Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     kan.liang@...ux.intel.com, peterz@...radead.org, mingo@...nel.org,
        linux-kernel@...r.kernel.org, acme@...nel.org, tglx@...utronix.de,
        namhyung@...nel.org, jolsa@...hat.com, ak@...ux.intel.com,
        yao.jin@...ux.intel.com, alexander.shishkin@...ux.intel.com,
        adrian.hunter@...el.com,
        "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
        "Ravi V. Shankar" <ravi.v.shankar@...el.com>,
        Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
Subject: Re: [PATCH V2 1/25] x86/cpufeatures: Enumerate Intel Hybrid
 Technology feature bit

On Wed, Mar 10, 2021 at 05:53:58PM +0100, Borislav Petkov wrote:
> On Wed, Mar 10, 2021 at 08:37:37AM -0800, kan.liang@...ux.intel.com wrote:
> > From: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> > 
> > Add feature enumeration to identify a processor with Intel Hybrid
> > Technology: one in which CPUs of more than one type are the same package.
> > On a hybrid processor, all CPUs support the same homogeneous (i.e.,
> > symmetric) instruction set. All CPUs enumerate the same features in CPUID.
> > Thus, software (user space and kernel) can run and migrate to any CPU in
> > the system as well as utilize any of the enumerated features without any
> > change or special provisions. The main difference among CPUs in a hybrid
> > processor are power and performance properties.
> > 
> > Cc: Andi Kleen <ak@...ux.intel.com>
> > Cc: Kan Liang <kan.liang@...ux.intel.com>
> > Cc: "Peter Zijlstra (Intel)" <peterz@...radead.org>
> > Cc: "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>
> > Cc: "Ravi V. Shankar" <ravi.v.shankar@...el.com>
> > Cc: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
> > Cc: linux-kernel@...r.kernel.org
> > Reviewed-by: Len Brown <len.brown@...el.com>
> > Reviewed-by: Tony Luck <tony.luck@...el.com>
> > Signed-off-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> > ---
> > Changes since v1 (as part of patchset for perf change for Alderlake)
> >  * None
> > 
> > Changes since v1 (in a separate posting):
> >  * Reworded commit message to clearly state what is Intel Hybrid
> >    Technology. Stress that all CPUs can run the same instruction
> >    set and support the same features.
> > ---
> >  arch/x86/include/asm/cpufeatures.h | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index cc96e26d69f7..e7cfc9eedf8d 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -374,6 +374,7 @@
> >  #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
> >  #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
> >  #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
> > +#define X86_FEATURE_HYBRID_CPU		(18*32+15) /* This part has CPUs of more than one type */
> 
> 							  /* "" This ...
> 
> unless you have a valid use case for "hybrid_cpu" being present there.

But this series provides the use case, right? Kan's patches handle PMU counters
that may differ cross types of CPUs. In patch 2, get_hybrid_params()
needs to check first if X86_FEATURE_HYBRID_CPU is enabled before
querying the hybrid parameters. Otherwise, we would need to rely on the
maximum level of CPUID, which may not be reliable.

Thanks and BR,
Ricardo

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