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Message-ID: <a04dcf6a-1152-8ef4-7ea4-00e67172c4b2@ti.com>
Date: Wed, 10 Mar 2021 15:54:27 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: Swapnil Kashinath Jakhade <sjakhade@...ence.com>,
Vinod Koul <vkoul@...nel.org>,
Rob Herring <robh+dt@...nel.org>, Peter Rosin <peda@...ntia.se>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>
Subject: Re: [PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk
out
Hi Swapnil,
On 09/03/21 7:51 pm, Swapnil Kashinath Jakhade wrote:
> Hi Kishon,
>
>> -----Original Message-----
>> From: Kishon Vijay Abraham I <kishon@...com>
>> Sent: Monday, February 22, 2021 4:53 PM
>> To: Kishon Vijay Abraham I <kishon@...com>; Vinod Koul
>> <vkoul@...nel.org>; Rob Herring <robh+dt@...nel.org>; Peter Rosin
>> <peda@...ntia.se>; Swapnil Kashinath Jakhade <sjakhade@...ence.com>
>> Cc: linux-kernel@...r.kernel.org; devicetree@...r.kernel.org; linux-
>> phy@...ts.infradead.org
>> Subject: [PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk out
>>
>> EXTERNAL MAIL
>>
>>
>> cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
>> reference clock. cmn_refclk_<p/m> can also be configured to output the
>> reference clock. Model this derived reference clock as a "clock" so that
>> platforms like AM642 EVM can enable it.
>>
>> This is used by PCIe to use the same refclk both in local SERDES
>> and remote device. Add support here to drive refclk out.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
>> ---
>> drivers/phy/cadence/phy-cadence-torrent.c | 202 +++++++++++++++++++++-
>> 1 file changed, 199 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
>> b/drivers/phy/cadence/phy-cadence-torrent.c
>> index f310e15d94cb..07eebdd90d4b 100644
>> --- a/drivers/phy/cadence/phy-cadence-torrent.c
>> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
>> @@ -7,7 +7,9 @@
>> */
>>
>> #include <dt-bindings/phy/phy.h>
>> +#include <dt-bindings/phy/phy-cadence-torrent.h>
>> #include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> #include <linux/delay.h>
>> #include <linux/err.h>
>> #include <linux/io.h>
>> @@ -76,6 +78,8 @@
>> * register offsets from SD0801 PHY register block base (i.e MHDP
>> * register base + 0x500000)
>> */
>> +#define CMN_CDIAG_REFCLK_OVRD 0x004CU
>> +#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
>
> Nitpick, this can be added sequentially.
>
>> #define CMN_SSM_BANDGAP_TMR 0x0021U
>> #define CMN_SSM_BIAS_TMR 0x0022U
>> #define CMN_PLLSM0_PLLPRE_TMR 0x002AU
>> @@ -206,6 +210,8 @@
>> #define RX_DIAG_ACYA 0x01FFU
>>
>> /* PHY PCS common registers */
>> +#define PHY_PIPE_CMN_CTRL1 0x0000U
>> +#define PHY_ISO_CMN_CTRL 0x0008U
>> #define PHY_PLL_CFG 0x000EU
>> #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
>> #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
>> @@ -216,6 +222,10 @@
>> #define PHY_PMA_CMN_CTRL2 0x0001U
>> #define PHY_PMA_PLL_RAW_CTRL 0x0003U
>>
>> +static const char * const clk_names[] = {
>> + [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
>> +};
>> +
>> static const struct reg_field phy_pll_cfg =
>> REG_FIELD(PHY_PLL_CFG, 0, 1);
>>
>> @@ -231,6 +241,36 @@ static const struct reg_field phy_pma_pll_raw_ctrl =
>> static const struct reg_field phy_reset_ctrl =
>> REG_FIELD(PHY_RESET, 8, 8);
>>
>> +#define REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG 2
>
> This could be reduced just to REFCLK_OUT_NUM_PCS_CONFIG, but up to you.
> Same below.
>
>> +
>> +enum cdns_torrent_refclk_out_pcs {
>> + PHY_ISO_CMN_CTRL_8,
>> + PHY_PIPE_CMN_CTRL1_0,
>> +};
>> +
>> +#define REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG 5
>> +
>> +enum cdns_torrent_refclk_out_cmn {
>> + CMN_CDIAG_REFCLK_OVRD_4,
>> + CMN_CDIAG_REFCLK_DRV0_CTRL_1,
>> + CMN_CDIAG_REFCLK_DRV0_CTRL_4,
>> + CMN_CDIAG_REFCLK_DRV0_CTRL_5,
>> + CMN_CDIAG_REFCLK_DRV0_CTRL_6,
>> +};
>> +
>> +static const struct reg_field refclk_out_pcs_cfg[] = {
>> + [PHY_ISO_CMN_CTRL_8] = REG_FIELD(PHY_ISO_CMN_CTRL, 8,
>> 8),
>> + [PHY_PIPE_CMN_CTRL1_0] = REG_FIELD(PHY_PIPE_CMN_CTRL1,
>> 0, 0),
>> +};
>> +
>> +static const struct reg_field refclk_out_cmn_cfg[] = {
>> + [CMN_CDIAG_REFCLK_OVRD_4] =
>> REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4),
>> + [CMN_CDIAG_REFCLK_DRV0_CTRL_1] =
>> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
>> + [CMN_CDIAG_REFCLK_DRV0_CTRL_4] =
>> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
>> + [CMN_CDIAG_REFCLK_DRV0_CTRL_5] =
>> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
>> + [CMN_CDIAG_REFCLK_DRV0_CTRL_6] =
>> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
>> +};
>> +
>> enum cdns_torrent_phy_type {
>> TYPE_NONE,
>> TYPE_DP,
>> @@ -279,6 +319,8 @@ struct cdns_torrent_phy {
>> struct regmap_field *phy_pma_cmn_ctrl_2;
>> struct regmap_field *phy_pma_pll_raw_ctrl;
>> struct regmap_field *phy_reset_ctrl;
>> + struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1];
>> + struct clk_onecell_data clk_data;
>> };
>>
>> enum phy_powerstate {
>> @@ -288,6 +330,16 @@ enum phy_powerstate {
>> POWERSTATE_A3 = 3,
>> };
>>
>> +struct cdns_torrent_derived_refclk {
>> + struct clk_hw hw;
>> + struct regmap_field
>> *pcs_fields[REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG];
>> + struct regmap_field
>> *cmn_fields[REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG];
>> + struct clk_init_data clk_data;
>> +};
>> +
>> +#define to_cdns_torrent_derived_refclk(_hw) \
>> + container_of(_hw, struct
>> cdns_torrent_derived_refclk, hw)
>> +
>> static int cdns_torrent_phy_init(struct phy *phy);
>> static int cdns_torrent_dp_init(struct phy *phy);
>> static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
>> @@ -1604,6 +1656,111 @@ static int cdns_torrent_dp_run(struct
>> cdns_torrent_phy *cdns_phy, u32 num_lanes)
>> return ret;
>> }
>>
>> +static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
>> +{
>> + struct cdns_torrent_derived_refclk *derived_refclk =
>> to_cdns_torrent_derived_refclk(hw);
>> +
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
>> + regmap_field_write(derived_refclk-
>>> cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1);
>> + regmap_field_write(derived_refclk-
>>> pcs_fields[PHY_PIPE_CMN_CTRL1_0], 1);
>> + regmap_field_write(derived_refclk-
>>> pcs_fields[PHY_ISO_CMN_CTRL_8], 1);
>> +
>> + return 0;
>> +}
>> +
>> +static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
>> +{
>> + struct cdns_torrent_derived_refclk *derived_refclk =
>> to_cdns_torrent_derived_refclk(hw);
>> +
>> + regmap_field_write(derived_refclk-
>>> pcs_fields[PHY_ISO_CMN_CTRL_8], 0);
>> +}
>> +
>
> PHY_ISO_CMN_CTRL is a PHY isolation register. Not sure, but is this correct
> to control phy_en_refclk to enable/disable refclk output from here?
hmm.. I see this is used to drive phy_en_refclk when in ISOLATION mode.
Given that we are not selecting to operate in isolation mode, this
shouldn't be required.
This was present in the sequence given by HW team but maybe it's enabled
for some debugging.
I've also verified PCIe works without this configuration. I'll repost
without this configuration and also check with HW team on why it was added.
Thanks
Kishon
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