linux-kernel - [PATCH 1/3] dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper

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Message-ID: <20210310112745.3445-2-kishon@ti.com>
Date:   Wed, 10 Mar 2021 16:57:43 +0530
From:   Kishon Vijay Abraham I <kishon@...com>
To:     Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Peter Rosin <peda@...ntia.se>,
        Swapnil Jakhade <sjakhade@...ence.com>
CC:     <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        Aswath Govindraju <a-govindraju@...com>,
        Nishanth Menon <nm@...com>, Lokesh Vutla <lokeshvutla@...com>
Subject: [PATCH 1/3] dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper

Add bindings for AM64 SERDES Wrapper.

Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
---
 .../bindings/phy/ti,phy-j721e-wiz.yaml        |  4 ++++
 include/dt-bindings/phy/phy-ti.h              | 21 +++++++++++++++++++
 2 files changed, 25 insertions(+)
 create mode 100644 include/dt-bindings/phy/phy-ti.h

diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index bbbd85501ada..57e1d013a502 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -15,6 +15,7 @@ properties:
     enum:
       - ti,j721e-wiz-16g
       - ti,j721e-wiz-10g
+      - ti,am64-wiz-10g
 
   power-domains:
     maxItems: 1
@@ -42,6 +43,9 @@ properties:
   "#reset-cells":
     const: 1
 
+  "#clock-cells":
+    const: 1
+
   ranges: true
 
   assigned-clocks:
diff --git a/include/dt-bindings/phy/phy-ti.h b/include/dt-bindings/phy/phy-ti.h
new file mode 100644
index 000000000000..ad955d3a56b4
--- /dev/null
+++ b/include/dt-bindings/phy/phy-ti.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for TI SERDES.
+ */
+
+#ifndef _DT_BINDINGS_TI_SERDES
+#define _DT_BINDINGS_TI_SERDES
+
+/* Clock index for output clocks from WIZ */
+
+/* MUX Clocks */
+#define TI_WIZ_PLL0_REFCLK	0
+#define TI_WIZ_PLL1_REFCLK	1
+#define TI_WIZ_REFCLK_DIG	2
+
+/* Reserve index here for future additions */
+
+/* MISC Clocks */
+#define TI_WIZ_PHY_EN_REFCLK	16
+
+#endif /* _DT_BINDINGS_TI_SERDES */
-- 
2.17.1