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Message-ID: <20210310112745.3445-4-kishon@ti.com>
Date:   Wed, 10 Mar 2021 16:57:45 +0530
From:   Kishon Vijay Abraham I <kishon@...com>
To:     Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Peter Rosin <peda@...ntia.se>,
        Swapnil Jakhade <sjakhade@...ence.com>
CC:     <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        Aswath Govindraju <a-govindraju@...com>,
        Nishanth Menon <nm@...com>, Lokesh Vutla <lokeshvutla@...com>
Subject: [PATCH 3/3] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC

AM64 has a single lane SERDES which can be configured to be used
with either PCIe or USB. Define the possilbe values for the SERDES
function in AM64 SoC here.

Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
Acked-by: Peter Rosin <peda@...ntia.se>
Acked-by: Rob Herring <robh@...nel.org>
---
 include/dt-bindings/mux/ti-serdes.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index 9047ec6bd3cf..d417b9268b16 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -90,4 +90,9 @@
 #define J7200_SERDES0_LANE3_USB			0x2
 #define J7200_SERDES0_LANE3_IP4_UNUSED		0x3
 
+/* AM64 */
+
+#define AM64_SERDES0_LANE0_PCIE0		0x0
+#define AM64_SERDES0_LANE0_USB			0x1
+
 #endif /* _DT_BINDINGS_MUX_TI_SERDES */
-- 
2.17.1

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