| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 11 Mar 2021 17:47:45 +0800
From: Jianjun Wang <jianjun.wang@...iatek.com>
To: Marc Zyngier <maz@...nel.org>
CC: Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Ryder Lee <ryder.lee@...iatek.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
"Matthias Brugger" <matthias.bgg@...il.com>,
<linux-pci@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
"Sj Huang" <sj.huang@...iatek.com>, <youlin.pei@...iatek.com>,
<chuanjia.liu@...iatek.com>, <qizhong.cheng@...iatek.com>,
<sin_jieyang@...iatek.com>, <drinkcat@...omium.org>,
<Rex-BC.Chen@...iatek.com>, <anson.chuang@...iatek.com>
Subject: Re: [v8,5/7] PCI: mediatek-gen3: Add MSI support
On Wed, 2021-03-10 at 09:41 +0000, Marc Zyngier wrote:
> On Wed, 10 Mar 2021 06:48:49 +0000,
> Jianjun Wang <jianjun.wang@...iatek.com> wrote:
> > > > +static struct irq_chip mtk_msi_irq_chip = {
> > > > + .name = "MSI",
> > > > + .irq_enable = mtk_pcie_irq_unmask,
> > > > + .irq_disable = mtk_pcie_irq_mask,
> > >
> > > Same comment as for the previous patch: enable/disable serve no
> > > purpose here.
> >
> > Replied in the previous patch, the enable/disable callback is used when
> > the system suspend/resume.
>
> As I said, your suspend/resume should be self contained, and not rely
> on the irq subsystem to restore a viable state.
OK, I will try to find another way to save and restore the enabled state
of interrupts when the system suspend/resume.
>
> [...]
>
> > > > @@ -408,6 +677,14 @@ static void mtk_pcie_irq_handler(struct irq_desc *desc)
> > > > generic_handle_irq(virq);
> > > > }
> > > >
> > > > + irq_bit = PCIE_MSI_SHIFT;
> > > > + for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
> > > > + PCIE_MSI_SHIFT) {
> > > > + mtk_pcie_msi_handler(port, irq_bit - PCIE_MSI_SHIFT);
> > > > +
> > > > + writel_relaxed(BIT(irq_bit), port->base + PCIE_INT_STATUS_REG);
> > >
> > > Isn't this write the same thing you have for EOI in the INTx case?
> > > While I could understand your description in that case (this is a
> > > resampling operation), I don't get what this does here. Either this is
> > > also an EOI, but your initial description doesn't make sense, or it is
> > > an Ack, and it should be moved to the right place.
> > >
> > > Which one is it?
> >
> > I think it should be an EOI which used to clear the interrupt status of
> > a single set in the PCIe intc field, maybe I should move it to the end
> > of the mtk_pcie_msi_handler() function.
>
> I doubt this is an EOI. If, as I suspect, it instructs the HW to clear
> the bit so that new pending bits can be recorded, it must take place
> *before* the interrupt is handled, or you may lose MSIs in the
> interval between the handling of the interrupt and the clearing of the
> pending bit. To satisfy this requirement, this should be an ACK, which
> is consistent with the way most MSI controllers such as this one work.
These bits are similar with the interrupt status of INTx, and the
interrupt status will remain until all the status of the corresponding
set are cleared. There is a while loop in mtk_pcie_msi_handler() which
is used to continuously polling and ACK the status of the MSI set, I
think the MSI may not be lose in this case.
>
> >
> > +-----+
> > | GIC |
> > +-----+
> > ^
> > |
> > port->irq
> > |
> > +-+-+-+-+-+-+-+-+
> > |0|1|2|3|4|5|6|7| (PCIe intc)
> > +-+-+-+-+-+-+-+-+
> > ^ ^ ^
> > | | ... |
> > +-------+ +------+ +-----------+
> > | | |
> > +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
> > |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
> > +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
> > ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
> > | | | | | | | | | | | | (MSI vectors)
> > | | | | | | | | | | | |
> >
> > (MSI SET0) (MSI SET1) ... (MSI SET7)
> >
> > I would like to ask another question. In this interrupt architecture, we
> > cannot implement an affinity for PCIe interrupts, so we return a
> > negative value in the mtk_pcie_set_affinity callback as follows:
> >
> > +static int mtk_pcie_set_affinity(struct irq_data *data,
> > + const struct cpumask *mask, bool force)
> > +{
> > + return -EINVAL;
> > +}
> >
> > But there will always be error logs when hotplug a CPU:
> >
> > ~ # echo 0 > /sys/devices/system/cpu/cpu1/online
> > [ 93.633059] IRQ255: set affinity failed(-22).
> > [ 93.633624] IRQ256: set affinity failed(-22).
> > [ 93.634222] CPU1: shutdown
> > [ 93.634586] psci: CPU1 killed (polled 0 ms)
> >
> > Or when the system suspends:
> >
> > ~ # echo mem > /sys/power/state
> > [ 93.635145] cpuhp: cpu_off cluster=0, cpu=1
> > [ 169.835653] PM: suspend entry (deep)
> > [ 169.836717] Filesystems sync: 0.000 seconds
> > [ 169.837924] Freezing user space processes ... (elapsed 0.001 seconds)
> > done.
> > [ 169.839922] OOM killer disabled.
> > [ 169.840336] Freezing remaining freezable tasks ... (elapsed 0.001
> > seconds) done.
> > [ 169.844715] Disabling non-boot CPUs ...
> > [ 169.846443] IRQ255: set affinity failed(-22).
> > [ 169.847002] IRQ256: set affinity failed(-22).
> > [ 169.847586] CPU2: shutdown
> > [ 169.847943] psci: CPU2 killed (polled 0 ms)
> > [ 169.848489] cpuhp: cpu_off cluster=0, cpu=2
> > [ 169.850285] IRQ255: set affinity failed(-22).
> > [ 169.851369] IRQ256: set affinity failed(-22).
> > ...
> >
> > Sometimes this can cause misunderstandings to users, do we have a chance
> > to prevent this error log?
>
> No. This HW doesn't allow MSIs to be individually retargeted, and the
> kernel isn't happy about that. That's one of the many reasons why
> hiding MSIs behind a mux (or two in your case) is a *very bad idea*.
>
> Thanks,
>
> M.
>
Powered by blists - more mailing lists