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Message-ID: <ce818341-ed33-cd8c-5c06-65147f510c4d@intel.com>
Date:   Sun, 14 Mar 2021 16:22:03 -0700
From:   Dave Hansen <dave.hansen@...el.com>
To:     Yu Zhao <yuzhao@...gle.com>, linux-mm@...ck.org
Cc:     Alex Shi <alex.shi@...ux.alibaba.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Hillf Danton <hdanton@...a.com>,
        Johannes Weiner <hannes@...xchg.org>,
        Joonsoo Kim <iamjoonsoo.kim@....com>,
        Matthew Wilcox <willy@...radead.org>,
        Mel Gorman <mgorman@...e.de>, Michal Hocko <mhocko@...e.com>,
        Roman Gushchin <guro@...com>, Vlastimil Babka <vbabka@...e.cz>,
        Wei Yang <richard.weiyang@...ux.alibaba.com>,
        Yang Shi <shy828301@...il.com>,
        Ying Huang <ying.huang@...el.com>,
        linux-kernel@...r.kernel.org, page-reclaim@...gle.com
Subject: Re: [PATCH v1 06/14] mm, x86: support the access bit on non-leaf PMD
 entries

On 3/12/21 11:57 PM, Yu Zhao wrote:
> Some architectures support the accessed bit on non-leaf PMD entries
> (parents) in addition to leaf PTE entries (children) where pages are
> mapped, e.g., x86_64 sets the accessed bit on a parent when using it
> as part of linear-address translation [1]. Page table walkers who are
> interested in the accessed bit on children can take advantage of this:
> they do not need to search the children when the accessed bit is not
> set on a parent, given that they have previously cleared the accessed
> bit on this parent in addition to its children.

I'd like to hear a *LOT* more about how this is going to be used.

The one part of this which is entirely missing is the interaction with
the TLB and mid-level paging structure caches.  The CPU is pretty
aggressive about setting no-leaf accessed bits when TLB entries are
created.  This *looks* to be depending on that behavior, but it would be
nice to spell it out explicitly.

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