linux-kernel - Re: [PATCH 1/3] arm64: dts: qcom: sm8150: add other QUP nodes

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Message-ID: <CAH=2Ntz71eezQrELqgjZu+mMvS5ANSsupyUYR6QU6-VS99K-Sw@mail.gmail.com>
Date:   Tue, 16 Mar 2021 00:47:46 +0530
From:   Bhupesh Sharma <bhupesh.sharma@...aro.org>
To:     Caleb Connolly <caleb@...nolly.tech>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] arm64: dts: qcom: sm8150: add other QUP nodes

Hello Caleb,

On Wed, 10 Mar 2021 at 22:02, Caleb Connolly <caleb@...nolly.tech> wrote:
>
> Add the first and third qupv3 nodes used to hook
> up peripherals on some devices.
>
> Signed-off-by: Caleb Connolly <caleb@...nolly.tech>
> ---
>  arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index e5bb17bc2f46..03e05d98daf2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -577,6 +577,18 @@ gcc: clock-controller@...000 {
>                                  <&sleep_clk>;
>                 };
>
> +               qupv3_id_0: geniqup@...000 {
> +                       compatible = "qcom,geni-se-qup";
> +                       reg = <0x0 0x008c0000 0x0 0x6000>;
> +                       clock-names = "m-ahb", "s-ahb";
> +                       clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> +                                <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       status = "disabled";
> +               };
> +
>                 qupv3_id_1: geniqup@...000 {
>                         compatible = "qcom,geni-se-qup";
>                         reg = <0x0 0x00ac0000 0x0 0x6000>;
> @@ -598,6 +610,19 @@ uart2: serial@...000 {
>                         };
>                 };
>
> +               qupv3_id_2: geniqup@...000 {
> +                       compatible = "qcom,geni-se-qup";
> +                       reg = <0x0 0x00cc0000 0x0 0x6000>;
> +
> +                       clock-names = "m-ahb", "s-ahb";
> +                       clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
> +                                <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +                       status = "disabled";
> +               };
> +
>                 config_noc: interconnect@...0000 {
>                         compatible = "qcom,sm8150-config-noc";
>                         reg = <0 0x01500000 0 0x7400>;

LGTM, so:
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>