linux-kernel - [PATCH 2/9] watchdog: of_xilinx

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Date:   Mon, 15 Mar 2021 16:16:47 +0530
From:   Srinivas Neeli <srinivas.neeli@...inx.com>
To:     <linux@...ck-us.net>, <michal.simek@...inx.com>,
        <shubhrajyoti.datta@...inx.com>, <sgoud@...inx.com>
CC:     <wim@...ux-watchdog.org>, <linux-watchdog@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <git@...inx.com>,
        Srinivas Goud <srinivas.goud@...inx.com>,
        Srinivas Neeli <srinivas.neeli@...inx.com>
Subject: [PATCH 2/9] watchdog: of_xilinx_wdt: Used BIT macro

From: Srinivas Goud <srinivas.goud@...inx.com>

Used BIT macro instead of mask value.

Signed-off-by: Srinivas Goud <srinivas.goud@...inx.com>
Signed-off-by: Michal Simek <michal.simek@...inx.com>
Signed-off-by: Srinivas Neeli <srinivas.neeli@...inx.com>
---
 drivers/watchdog/of_xilinx_wdt.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/watchdog/of_xilinx_wdt.c b/drivers/watchdog/of_xilinx_wdt.c
index 00549164b3d7..0d7df2370db7 100644
--- a/drivers/watchdog/of_xilinx_wdt.c
+++ b/drivers/watchdog/of_xilinx_wdt.c
@@ -24,12 +24,12 @@
 #define XWT_TBR_OFFSET      0x8 /* Timebase Register Offset */
 
 /* Control/Status Register Masks  */
-#define XWT_CSR0_WRS_MASK   0x00000008 /* Reset status */
-#define XWT_CSR0_WDS_MASK   0x00000004 /* Timer state  */
-#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
+#define XWT_CSR0_WRS_MASK	BIT(3) /* Reset status */
+#define XWT_CSR0_WDS_MASK	BIT(2) /* Timer state  */
+#define XWT_CSR0_EWDT1_MASK	BIT(1) /* Enable bit 1 */
 
 /* Control/Status Register 0/1 bits  */
-#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
+#define XWT_CSRX_EWDT2_MASK	BIT(0) /* Enable bit 2 */
 
 /* SelfTest constants */
 #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
-- 
2.7.4