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Message-ID: <YFDlbKD4Q13lDmM3@smile.fi.intel.com>
Date: Tue, 16 Mar 2021 19:05:48 +0200
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Jan Kiszka <jan.kiszka@...mens.com>, linux-gpio@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Andy Shevchenko <andy@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <bgolaszewski@...libre.com>
Subject: Re: [PATCH v4 2/2] gpio: sch: Hook into ACPI SCI handler to catch
GPIO edge events
On Tue, Mar 16, 2021 at 06:26:13PM +0200, Andy Shevchenko wrote:
> From: Jan Kiszka <jan.kiszka@...mens.com>
>
> Neither the ACPI description on the Quark platform provides the required
> information is to do establish generic handling nor hardware capable of
> doing it. According to the datasheet the hardware can generate SCI events.
> Therefore, we need to hook from the driver directly into SCI handler of
> the ACPI subsystem in order to catch and report GPIO-related events.
> Validated on the Quark-based IOT2000 platform.
This depends on the test by Jan or somebody with the same hardware available.
> +static u32 sch_gpio_sci_handler(void *context)
> +{
> + struct sch_gpio *sch = context;
> + struct gpio_chip *gc = &sch->chip;
> + unsigned long core_status, resume_status;
> + unsigned long pending;
> + int offset;
> + core_status = inl(sch->iobase + GTS + 0x00);
> + resume_status = inl(sch->iobase + GTS + 0x20);
> +
> + pending = (resume_status << sch->resume_base) | core_status;
> +
> + for_each_set_bit(offset, &pending, sch->chip.ngpio)
> + generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));
> +
> + outl(core_status, sch->iobase + GTS + 0x00);
> + outl(resume_status, sch->iobase + GTS + 0x20);
I guess this still needs to be protected by spin_lock.
> + return pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
> +}
...
Also I am in doubt that we need to instantiate an IRQ chip if the ACPI SCI
handler registration fails. But I don't know what is better approach here, to
NULL the pointer, or try to register handler before we will have an IRQ chip in
place. Any recommendations?
--
With Best Regards,
Andy Shevchenko
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