lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <b0ec8d05-acbc-3021-2e74-684d119de2db@linux.intel.com>
Date:   Wed, 17 Mar 2021 20:17:52 +0800
From:   "Jin, Yao" <yao.jin@...ux.intel.com>
To:     Jiri Olsa <jolsa@...hat.com>
Cc:     acme@...nel.org, jolsa@...nel.org, peterz@...radead.org,
        mingo@...hat.com, alexander.shishkin@...ux.intel.com,
        Linux-kernel@...r.kernel.org, ak@...ux.intel.com,
        kan.liang@...el.com, yao.jin@...el.com
Subject: Re: [PATCH v2 11/27] perf parse-events: Support hardware events
 inside PMU

Hi Jiri,

On 3/17/2021 6:06 PM, Jiri Olsa wrote:
> On Wed, Mar 17, 2021 at 10:12:03AM +0800, Jin, Yao wrote:
>>
>>
>> On 3/16/2021 10:04 PM, Jiri Olsa wrote:
>>> On Tue, Mar 16, 2021 at 09:49:42AM +0800, Jin, Yao wrote:
>>>
>>> SNIP
>>>
>>>>
>>>>    Performance counter stats for 'system wide':
>>>>
>>>>          136,655,302      cpu_core/branch-instructions/
>>>>
>>>>          1.003171561 seconds time elapsed
>>>>
>>>> So we need special rules for both cycles and branches.
>>>>
>>>> The worse thing is, we also need to process the hardware cache events.
>>>>
>>>> # ./perf stat -e cpu_core/LLC-loads/
>>>> event syntax error: 'cpu_core/LLC-loads/'
>>>>                                 \___ unknown term 'LLC-loads' for pmu 'cpu_core'
>>>>
>>>> valid terms: event,pc,edge,offcore_rsp,ldlat,inv,umask,frontend,cmask,config,config1,config2,name,period,percore
>>>>
>>>> Initial error:
>>>> event syntax error: 'cpu_core/LLC-loads/'
>>>>                                 \___ unknown term 'LLC-loads' for pmu 'cpu_core'
>>>>
>>>> If we use special rules for establishing all event mapping, that looks too much. :(
>>>
>>> hmmm but wait, currently we do not support events like this:
>>>
>>>     'cpu/cycles/'
>>>     'cpu/branches/'
>>>
>>> the pmu style accepts only 'events' or 'format' terms within //
>>>
>>> we made hw events like 'cycles','instructions','branches' special
>>> to be used without the pmu
>>>
>>> so why do we need to support cpu_code/cycles/ ?
>>>
>>> jirka
>>>
>>
>> Actually we have to support pmu style event for hybrid platform.
>>
>> User may want to enable the events from specified pmus and also with flexible grouping.
>>
>> For example,
>>
>> perf stat -e '{cpu_core/cycles/,cpu_core/instructions/}' -e '{cpu_atom/cycles/,cpu_atom/instructions/}'
>>
>> This usage is common and reasonable. So I think we may need to support pmu style events.
> 
> sure, but we don't support 'cpu/cycles/' but we support 'cpu/cpu-cycles/'
> why do you insist on supporting cpu_core/cycles/ ?
> 
> jirka
> 

I'm OK to only support 'cpu_core/cpu-cycles/' or 'cpu_atom/cpu-cycles/'. But what would we do for 
cache event?

'perf stat -e LLC-loads' is OK, but 'perf stat -e cpu/LLC-loads/' is not supported currently.

For hybrid platform, user may only want to enable the LLC-loads on core CPUs or on atom CPUs. That's 
reasonable. While if we don't support the pmu style event, how to satisfy this requirement?

If we can support the pmu style event, we can also use the same way for cpu_core/cycles/. At least 
it's not a bad thing, right? :)

Thanks
Jin Yao

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ