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Message-Id: <20210317173202.107519-3-benjamin.gaignard@collabora.com>
Date: Wed, 17 Mar 2021 18:31:51 +0100
From: Benjamin Gaignard <benjamin.gaignard@...labora.com>
To: ezequiel@...labora.com, p.zabel@...gutronix.de, mchehab@...nel.org,
robh+dt@...nel.org, shawnguo@...nel.org, s.hauer@...gutronix.de,
festevam@...il.com, lee.jones@...aro.org,
gregkh@...uxfoundation.org, mripard@...nel.org,
paul.kocialkowski@...tlin.com, wens@...e.org,
jernej.skrabec@...l.net, hverkuil-cisco@...all.nl,
emil.l.velikov@...il.com
Cc: kernel@...gutronix.de, linux-imx@....com,
linux-media@...r.kernel.org, linux-rockchip@...ts.infradead.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devel@...verdev.osuosl.org,
kernel@...labora.com,
Benjamin Gaignard <benjamin.gaignard@...labora.com>
Subject: [PATCH v5 02/13] dt-bindings: media: nxp,imx8mq-vpu: Update the bindings for G2 support
Introducing G2 hevc video decoder lead to modify the bindings to allow
to get one node per VPUs.
VPUs share one hardware control block which is provided as a phandle on
an syscon.
Each node got now one reg and one interrupt.
Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
To be compatible with older DT the driver is still capable to use 'ctrl'
reg-name even if it is deprecated now.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@...labora.com>
---
version 5:
- This version doesn't break the backward compatibilty between kernel
and DT.
.../bindings/media/nxp,imx8mq-vpu.yaml | 53 ++++++++++++-------
1 file changed, 34 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
index 762be3f96ce9..79502fc8bde5 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
@@ -15,22 +15,18 @@ description:
properties:
compatible:
- const: nxp,imx8mq-vpu
+ oneOf:
+ - const: nxp,imx8mq-vpu
+ - const: nxp,imx8mq-vpu-g2
reg:
- maxItems: 3
-
- reg-names:
- items:
- - const: g1
- - const: g2
- - const: ctrl
+ maxItems: 1
interrupts:
- maxItems: 2
+ maxItems: 1
interrupt-names:
- items:
+ oneOf:
- const: g1
- const: g2
@@ -46,14 +42,18 @@ properties:
power-domains:
maxItems: 1
+ nxp,imx8mq-vpu-ctrl:
+ description: Specifies a phandle to syscon VPU hardware control block
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+
required:
- compatible
- reg
- - reg-names
- interrupts
- interrupt-names
- clocks
- clock-names
+ - nxp,imx8mq-vpu-ctrl
additionalProperties: false
@@ -62,18 +62,33 @@ examples:
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
- vpu: video-codec@...00000 {
+ vpu_ctrl: syscon@...20000 {
+ compatible = "nxp,imx8mq-vpu-ctrl", "syscon";
+ reg = <0x38320000 0x10000>;
+ };
+
+ vpu_g1: video-codec@...00000 {
compatible = "nxp,imx8mq-vpu";
- reg = <0x38300000 0x10000>,
- <0x38310000 0x10000>,
- <0x38320000 0x10000>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g1", "g2";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "g2", "bus";
+ power-domains = <&pgc_vpu>;
+ nxp,imx8mq-vpu-ctrl = <&vpu_ctrl>;
+ };
+
+ vpu_g2: video-codec@...10000 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
clock-names = "g1", "g2", "bus";
power-domains = <&pgc_vpu>;
+ nxp,imx8mq-vpu-ctrl = <&vpu_ctrl>;
};
--
2.25.1
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