linux-kernel - Re: [PATCH net,v2] net: dsa: mt7530: setup core clock even in TRGMII mode

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20210319102555.Horde.jeA-oYm4tfkVqKj-gnqxRoo@www.vdorst.com>
Date:   Fri, 19 Mar 2021 10:25:55 +0000
From:   René van Dorst <opensource@...rst.com>
To:     Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>
Cc:     Sean Wang <sean.wang@...iatek.com>,
        Landen Chao <Landen.Chao@...iatek.com>,
        Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        sander@...nheule.net, tsbogend@...ha.franken.de, john@...ozen.org,
        Frank Wunderlich <frank-w@...lic-files.de>
Subject: Re: [PATCH net,v2] net: dsa: mt7530: setup core clock even in
 TRGMII mode

Quoting Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>:

> A recent change to MIPS ralink reset logic made it so mt7530 actually
> resets the switch on platforms such as mt7621 (where bit 2 is the reset
> line for the switch). That exposed an issue where the switch would not
> function properly in TRGMII mode after a reset.
>
> Reconfigure core clock in TRGMII mode to fix the issue.
>
> Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
>
> Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>
> ---
>  drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++---------------------
>  1 file changed, 25 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index f06f5fa2f898..9871d7cff93a 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch *ds,  
> phy_interface_t interface)
>  			     TD_DM_DRVP(8) | TD_DM_DRVN(8));
>
>  	/* Setup core clock for MT7530 */
> -	if (!trgint) {
> -		/* Disable MT7530 core clock */
> -		core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> -
> -		/* Disable PLL, since phy_device has not yet been created
> -		 * provided for phy_[read,write]_mmd_indirect is called, we
> -		 * provide our own core_write_mmd_indirect to complete this
> -		 * function.
> -		 */
> -		core_write_mmd_indirect(priv,
> -					CORE_GSWPLL_GRP1,
> -					MDIO_MMD_VEND2,
> -					0);
> -
> -		/* Set core clock into 500Mhz */
> -		core_write(priv, CORE_GSWPLL_GRP2,
> -			   RG_GSWPLL_POSDIV_500M(1) |
> -			   RG_GSWPLL_FBKDIV_500M(25));
> +	/* Disable MT7530 core clock */
> +	core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
>
> -		/* Enable PLL */
> -		core_write(priv, CORE_GSWPLL_GRP1,
> -			   RG_GSWPLL_EN_PRE |
> -			   RG_GSWPLL_POSDIV_200M(2) |
> -			   RG_GSWPLL_FBKDIV_200M(32));
> -
> -		/* Enable MT7530 core clock */
> -		core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> -	}
> +	/* Disable PLL, since phy_device has not yet been created
> +	 * provided for phy_[read,write]_mmd_indirect is called, we
> +	 * provide our own core_write_mmd_indirect to complete this
> +	 * function.
> +	 */
> +	core_write_mmd_indirect(priv,
> +				CORE_GSWPLL_GRP1,
> +				MDIO_MMD_VEND2,
> +				0);
> +
> +	/* Set core clock into 500Mhz */
> +	core_write(priv, CORE_GSWPLL_GRP2,
> +		   RG_GSWPLL_POSDIV_500M(1) |
> +		   RG_GSWPLL_FBKDIV_500M(25));
> +
> +	/* Enable PLL */
> +	core_write(priv, CORE_GSWPLL_GRP1,
> +		   RG_GSWPLL_EN_PRE |
> +		   RG_GSWPLL_POSDIV_200M(2) |
> +		   RG_GSWPLL_FBKDIV_200M(32));
> +
> +	/* Enable MT7530 core clock */
> +	core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
>
>  	/* Setup the MT7530 TRGMII Tx Clock */
>  	core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> --
> 2.30.2

Hi Ilya,

Thanks for fixing this issue.

I remember that Frank also had an issue with TRGMII on his MT7623 ARM board.
I never found why it did not work but this may be also fix his issue  
on the MT7623 devices.

Added Frank to CC.

Tested on Ubiquiti ER-X-SFP (MT7621) with and without TRGMII mode enabled.

Tested-by: René van Dorst <opensource@...rst.com>

Greats,

René