linux-kernel - Re: [PATCH v4 00/11] KVM: x86/pmu: Guest Architectural LBR Enabling

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Message-ID: <c73abc8d-a67b-6a6d-b052-682b8cf32351@intel.com>
Date:   Mon, 22 Mar 2021 14:18:40 +0800
From:   "Xu, Like" <like.xu@...el.com>
To:     Paolo Bonzini <pbonzini@...hat.com>,
        Sean Christopherson <seanjc@...gle.com>
Cc:     Vitaly Kuznetsov <vkuznets@...hat.com>,
        Wanpeng Li <wanpengli@...cent.com>,
        Jim Mattson <jmattson@...gle.com>,
        Joerg Roedel <joro@...tes.org>, kvm@...r.kernel.org,
        x86@...nel.org, wei.w.wang@...el.com, linux-kernel@...r.kernel.org,
        Like Xu <like.xu@...ux.intel.com>
Subject: Re: [PATCH v4 00/11] KVM: x86/pmu: Guest Architectural LBR Enabling

Hi, do we have any comments on this patch set?

On 2021/3/14 23:52, Like Xu wrote:
> Hi geniuses,
>
> Please help review the new version of Arch LBR enabling patch set.
>
> The Architectural Last Branch Records (LBRs) is publiced
> in the 319433-040 release of Intel Architecture Instruction
> Set Extensions and Future Features Programming Reference[0].
> ---
> v3->v4 Changelog:
> - Add one more host patch to reuse ARCH_LBR_CTL_MASK;
> - Add reserve_lbr_buffers() instead of using GFP_ATOMIC;
> - Fia a bug in the arch_lbr_depth_is_valid();
> - Add LBR_CTL_EN to unify DEBUGCTLMSR_LBR and ARCH_LBR_CTL_LBREN;
> - Add vmx->host_lbrctlmsr to save/restore host values;
> - Add KVM_SUPPORTED_XSS to refactoring supported_xss;
> - Clear Arch_LBR ans its XSS bit if it's not supported;
> - Add negative testing to the related kvm-unit-tests;
> - Refine code and commit messages;
>
> Previous:
> https://lore.kernel.org/kvm/20210303135756.1546253-1-like.xu@linux.intel.com/
>
> Like Xu (11):
>    KVM: vmx/pmu: Add MSR_ARCH_LBR_DEPTH emulation for Arch LBR
>    KVM: vmx/pmu: Add MSR_ARCH_LBR_CTL emulation for Arch LBR
>    KVM: vmx/pmu: Add Arch LBR emulation and its VMCS field
>    KVM: x86: Expose Architectural LBR CPUID leaf
>    KVM: x86: Refine the matching and clearing logic for supported_xss
>    KVM: x86: Add XSAVE Support for Architectural LBRs
>
>   arch/x86/events/core.c           |   8 ++-
>   arch/x86/events/intel/bts.c      |   2 +-
>   arch/x86/events/intel/core.c     |   6 +-
>   arch/x86/events/intel/lbr.c      |  28 +++++----
>   arch/x86/events/perf_event.h     |   8 ++-
>   arch/x86/include/asm/msr-index.h |   1 +
>   arch/x86/include/asm/vmx.h       |   4 ++
>   arch/x86/kvm/cpuid.c             |  25 +++++++-
>   arch/x86/kvm/vmx/capabilities.h  |  25 +++++---
>   arch/x86/kvm/vmx/pmu_intel.c     | 103 ++++++++++++++++++++++++++++---
>   arch/x86/kvm/vmx/vmx.c           |  50 +++++++++++++--
>   arch/x86/kvm/vmx/vmx.h           |   4 ++
>   arch/x86/kvm/x86.c               |   6 +-
>   13 files changed, 227 insertions(+), 43 deletions(-)
>