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Date: Mon, 22 Mar 2021 16:00:15 +0530
From: Maulik Shah <mkshah@...eaurora.org>
To: swboyd@...omium.org, bjorn.andersson@...aro.org, maz@...nel.org
Cc: linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
robh+dt@...nel.org, dianders@...omium.org, rnayak@...eaurora.org,
lsrao@...eaurora.org, Maulik Shah <mkshah@...eaurora.org>,
devicetree@...r.kernel.org
Subject: [PATCH v2] dt-bindings: interrupt-controller: Convert bindings to yaml for qcom,pdc
This change converts PDC interrupt controller bindings to yaml.
Cc: devicetree@...r.kernel.org
Signed-off-by: Maulik Shah <mkshah@...eaurora.org>
---
This change depends on [1] which adds sc7280 compatible for PDC
Changes in v2:
- Document optional PDC's GIC interface reg
- Update example to mention optional reg.
[1] https://patchwork.kernel.org/project/linux-arm-msm/list/?series=449725
---
.../bindings/interrupt-controller/qcom,pdc.txt | 76 -----------------
.../bindings/interrupt-controller/qcom,pdc.yaml | 96 ++++++++++++++++++++++
2 files changed, 96 insertions(+), 76 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
deleted file mode 100644
index 98d89e5..0000000
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
+++ /dev/null
@@ -1,76 +0,0 @@
-PDC interrupt controller
-
-Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
-Power Domain Controller (PDC) that is on always-on domain. In addition to
-providing power control for the power domains, the hardware also has an
-interrupt controller that can be used to help detect edge low interrupts as
-well detect interrupts when the GIC is non-operational.
-
-GIC is parent interrupt controller at the highest level. Platform interrupt
-controller PDC is next in hierarchy, followed by others. Drivers requiring
-wakeup capabilities of their device interrupts routed through the PDC, must
-specify PDC as their interrupt controller and request the PDC port associated
-with the GIC interrupt. See example below.
-
-Properties:
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
- - "qcom,sc7180-pdc": For SC7180
- - "qcom,sc7280-pdc": For SC7280
- - "qcom,sdm845-pdc": For SDM845
- - "qcom,sdm8250-pdc": For SM8250
- - "qcom,sdm8350-pdc": For SM8350
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Specifies the base physical address for PDC hardware.
-
-- interrupt-cells:
- Usage: required
- Value type: <u32>
- Definition: Specifies the number of cells needed to encode an interrupt
- source.
- Must be 2.
- The first element of the tuple is the PDC pin for the
- interrupt.
- The second element is the trigger type.
-
-- interrupt-controller:
- Usage: required
- Value type: <bool>
- Definition: Identifies the node as an interrupt controller.
-
-- qcom,pdc-ranges:
- Usage: required
- Value type: <u32 array>
- Definition: Specifies the PDC pin offset and the number of PDC ports.
- The tuples indicates the valid mapping of valid PDC ports
- and their hwirq mapping.
- The first element of the tuple is the starting PDC port.
- The second element is the GIC hwirq number for the PDC port.
- The third element is the number of interrupts in sequence.
-
-Example:
-
- pdc: interrupt-controller@...0000 {
- compatible = "qcom,sdm845-pdc";
- reg = <0xb220000 0x30000>;
- qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- interrupt-controller;
- };
-
-DT binding of a device that wants to use the GIC SPI 514 as a wakeup
-interrupt, must do -
-
- wake-device {
- interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
- };
-
-In this case interrupt 514 would be mapped to port 2 on the PDC as defined by
-the qcom,pdc-ranges property.
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
new file mode 100644
index 0000000..8b4151c
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. PDC interrupt controller
+
+maintainers:
+ - Maulik Shah <mkshah@...eaurora.org>
+
+description: |
+ Qualcomm Technologies, Inc. SoCs based on the RPM Hardened architecture have a
+ Power Domain Controller (PDC) that is on always-on domain. In addition to
+ providing power control for the power domains, the hardware also has an
+ interrupt controller that can be used to help detect edge low interrupts as
+ well detect interrupts when the GIC is non-operational.
+
+ GIC is parent interrupt controller at the highest level. Platform interrupt
+ controller PDC is next in hierarchy, followed by others. Drivers requiring
+ wakeup capabilities of their device interrupts routed through the PDC, must
+ specify PDC as their interrupt controller and request the PDC port associated
+ with the GIC interrupt. See example below.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ # Should contain "qcom,<soc>-pdc" and "qcom,pdc"
+ - qcom,sc7180-pdc #For SC7180
+ - qcom,sc7280-pdc #For SC7280
+ - qcom,sdm845-pdc #For SDM845
+ - qcom,sm8250-pdc #For SM8250
+ - qcom,sm8350-pdc #For SM8350
+ - const: qcom,pdc
+
+ reg:
+ description: |
+ Specifies the base physical address for PDC hardware followed by optional
+ PDC's GIC interface registers that need to be configured for wakeup capable
+ GPIOs routed to the PDC.
+ minItems: 1
+ maxItems: 2
+
+ '#interrupt-cells':
+ # Specifies the number of cells needed to encode an interrupt.
+ # The first element of the tuple is the PDC pin for the interrupt.
+ # The second element is the trigger type.
+ const: 2
+
+ interrupt-controller: true
+
+ qcom,pdc-ranges:
+ description: |
+ Specifies the PDC pin offset and the number of PDC ports.
+ The tuples indicates the valid mapping of valid PDC ports
+ and their hwirq mapping.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: |
+ "a" The first element of the tuple is the starting PDC port.
+ - description: |
+ "b" The second element is the GIC SPI number for the PDC port.
+ - description: |
+ "c" The third element is the number of interrupts in sequence.
+
+required:
+ - compatible
+ - reg
+ - '#interrupt-cells'
+ - interrupt-controller
+ - qcom,pdc-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ pdc: interrupt-controller@...0000 {
+ compatible = "qcom,sdm845-pdc", "qcom,pdc";
+ reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
+ qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ # DT binding of a device that wants to use the GIC SPI 514 as a wakeup
+ # interrupt, must do -
+ # wake-device {
+ # interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
+ # };
+
+ # In this case interrupt 514 would be mapped to port 2 on the PDC as defined
+ # by the qcom,pdc-ranges property.
+...
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
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