linux-kernel - Re: (subset) [PATCH v5 00/19] coresight: Add support for ETE and TRBE

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Message-Id: <161651726490.2050093.5536833570808361940.b4-ty@kernel.org>
Date:   Tue, 23 Mar 2021 16:34:36 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     linux-arm-kernel@...ts.infradead.org,
        Suzuki K Poulose <suzuki.poulose@....com>
Cc:     leo.yan@...aro.org, catalin.marinas@....com,
        Linu Cherian <lcherian@...vell.com>,
        Will Deacon <will@...nel.org>, coresight@...ts.linaro.org,
        Peter Zilstra <peterz@...radead.org>,
        anshuman.khandual@....com, mike.leach@...aro.org,
        mathieu.poirier@...aro.org, linux-kernel@...r.kernel.org
Subject: Re: (subset) [PATCH v5 00/19] coresight: Add support for ETE and TRBE

On Tue, 23 Mar 2021 12:06:28 +0000, Suzuki K Poulose wrote:
> This series enables future IP trace features Embedded Trace Extension
> (ETE) and Trace Buffer Extension (TRBE). This series applies on
> v5.12-rc4 + some patches queued. A standalone tree is also available here [0].
> The queued patches (almost there) are included in this posting for
> the sake of constructing a tree from the posting.
> 
> ETE is the PE (CPU) trace unit for CPUs, implementing future
> architecture extensions. ETE overlaps with the ETMv4 architecture, with
> additions to support the newer architecture features and some restrictions
> on the supported features w.r.t ETMv4. The ETE support is added by extending
> the ETMv4 driver to recognise the ETE and handle the features as exposed by
> the TRCIDRx registers. ETE only supports system instructions access from the
> host CPU. The ETE could be integrated with a TRBE (see below), or with
> the legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same
> firmware description as the ETMs and requires a node per instance.
> 
> [...]

Applied to fixes, thanks!

[01/19] kvm: arm64: Hide system instruction access to Trace registers
        commit: 4af0afe252a2701732c317585f7c3ef6596b8f3d

Cheers,

	M.
-- 
Without deviation from the norm, progress is not possible.