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Message-ID: <20210323224826.GA1490612@robh.at.kernel.org>
Date: Tue, 23 Mar 2021 16:48:26 -0600
From: Rob Herring <robh@...nel.org>
To: Dmitry Osipenko <digetx@...il.com>
Cc: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Mark Brown <broonie@...nel.org>,
Paul Fertser <fercerpav@...il.com>,
Matt Merhar <mattmerhar@...tonmail.com>,
Peter Geis <pgwipeout@...il.com>,
Nicolas Chauvet <kwizart@...il.com>,
Viresh Kumar <vireshk@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
Michał Mirosław <mirq-linux@...e.qmqm.pl>,
Krzysztof Kozlowski <krzk@...nel.org>,
devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 3/6] dt-bindings: power: tegra: Add binding for core
power domain
On Sun, Mar 14, 2021 at 07:48:07PM +0300, Dmitry Osipenko wrote:
> All NVIDIA Tegra SoCs have a core power domain where majority of hardware
> blocks reside. Add binding for the core power domain.
>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> ---
> .../power/nvidia,tegra20-core-domain.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
>
> diff --git a/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
> new file mode 100644
> index 000000000000..4692489d780a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/power/nvidia,tegra20-core-domain.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra Core Power Domain
> +
> +maintainers:
> + - Dmitry Osipenko <digetx@...il.com>
> + - Jon Hunter <jonathanh@...dia.com>
> + - Thierry Reding <thierry.reding@...il.com>
> +
> +allOf:
> + - $ref: power-domain.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra20-core-domain
> + - nvidia,tegra30-core-domain
> +
> + operating-points-v2:
> + description:
> + Should contain level, voltages and opp-supported-hw property.
> + The supported-hw is a bitfield indicating SoC speedo or process
> + ID mask.
> +
> + "#power-domain-cells":
> + const: 0
> +
> + power-supply:
> + description:
> + Phandle to voltage regulator connected to the SoC Core power rail.
> +
> +required:
> + - compatible
> + - operating-points-v2
> + - "#power-domain-cells"
> + - power-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + power-domain {
> + compatible = "nvidia,tegra20-core-domain";
> + operating-points-v2 = <&opp_table>;
> + power-supply = <®ulator>;
> + #power-domain-cells = <0>;
AFAICT, there's no way to access this 'hardware'?
> + };
> --
> 2.30.2
>
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