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Message-ID: <67cc380019fd40d88d7a493b6cbc0852@hisilicon.com>
Date: Tue, 23 Mar 2021 23:21:09 +0000
From: "Song Bao Hua (Barry Song)" <song.bao.hua@...ilicon.com>
To: Tim Chen <tim.c.chen@...ux.intel.com>,
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Subject: RE: [RFC PATCH v5 4/4] scheduler: Add cluster scheduler level for x86
> -----Original Message-----
> From: Tim Chen [mailto:tim.c.chen@...ux.intel.com]
> Sent: Wednesday, March 24, 2021 11:51 AM
> To: Song Bao Hua (Barry Song) <song.bao.hua@...ilicon.com>;
> catalin.marinas@....com; will@...nel.org; rjw@...ysocki.net;
> vincent.guittot@...aro.org; bp@...en8.de; tglx@...utronix.de;
> mingo@...hat.com; lenb@...nel.org; peterz@...radead.org;
> dietmar.eggemann@....com; rostedt@...dmis.org; bsegall@...gle.com;
> mgorman@...e.de
> Cc: msys.mizuma@...il.com; valentin.schneider@....com;
> gregkh@...uxfoundation.org; Jonathan Cameron <jonathan.cameron@...wei.com>;
> juri.lelli@...hat.com; mark.rutland@....com; sudeep.holla@....com;
> aubrey.li@...ux.intel.com; linux-arm-kernel@...ts.infradead.org;
> linux-kernel@...r.kernel.org; linux-acpi@...r.kernel.org; x86@...nel.org;
> xuwei (O) <xuwei5@...wei.com>; Zengtao (B) <prime.zeng@...ilicon.com>;
> guodong.xu@...aro.org; yangyicong <yangyicong@...wei.com>; Liguozhu (Kenneth)
> <liguozhu@...ilicon.com>; linuxarm@...neuler.org; hpa@...or.com
> Subject: Re: [RFC PATCH v5 4/4] scheduler: Add cluster scheduler level for x86
>
>
>
> On 3/18/21 9:16 PM, Barry Song wrote:
> > From: Tim Chen <tim.c.chen@...ux.intel.com>
> >
> > There are x86 CPU architectures (e.g. Jacobsville) where L2 cahce
> > is shared among a cluster of cores instead of being exclusive
> > to one single core.
> >
> > To prevent oversubscription of L2 cache, load should be
> > balanced between such L2 clusters, especially for tasks with
> > no shared data.
> >
> > Also with cluster scheduling policy where tasks are woken up
> > in the same L2 cluster, we will benefit from keeping tasks
> > related to each other and likely sharing data in the same L2
> > cluster.
> >
> > Add CPU masks of CPUs sharing the L2 cache so we can build such
> > L2 cluster scheduler domain.
> >
> > Signed-off-by: Tim Chen <tim.c.chen@...ux.intel.com>
> > Signed-off-by: Barry Song <song.bao.hua@...ilicon.com>
>
>
> Barry,
>
> Can you also add this chunk to the patch.
> Thanks.
Sure, Tim, Thanks. I'll put that into patch 4/4 in v6.
>
> Tim
>
>
> diff --git a/arch/x86/include/asm/topology.h
> b/arch/x86/include/asm/topology.h
> index 2a11ccc14fb1..800fa48c9fcd 100644
> --- a/arch/x86/include/asm/topology.h
> +++ b/arch/x86/include/asm/topology.h
> @@ -115,6 +115,7 @@ extern unsigned int __max_die_per_package;
>
> #ifdef CONFIG_SMP
> #define topology_die_cpumask(cpu) (per_cpu(cpu_die_map, cpu))
> +#define topology_cluster_cpumask(cpu) (cpu_clustergroup_mask(cpu))
> #define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu))
> #define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu))
>
Thanks
Barry
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