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Message-ID: <62602598e7b742d09c581f3fc988e487@AcuMS.aculab.com>
Date:   Wed, 24 Mar 2021 16:38:31 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Robin Murphy' <robin.murphy@....com>,
        Yang Yingliang <yangyingliang@...wei.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     "catalin.marinas@....com" <catalin.marinas@....com>,
        "will@...nel.org" <will@...nel.org>,
        "guohanjun@...wei.com" <guohanjun@...wei.com>
Subject: RE: [PATCH 2/3] arm64: lib: improve copy performance when size is ge
 128 bytes

From: Robin Murphy
> Sent: 23 March 2021 12:09
> 
> On 2021-03-23 07:34, Yang Yingliang wrote:
> > When copy over 128 bytes, src/dst is added after
> > each ldp/stp instruction, it will cost more time.
> > To improve this, we only add src/dst after load
> > or store 64 bytes.
> 
> This breaks the required behaviour for copy_*_user(), since the fault
> handler expects the base address to be up-to-date at all times. Say
> you're copying 128 bytes and fault on the 4th store, it should return 80
> bytes not copied; the code below would return 128 bytes not copied, even
> though 48 bytes have actually been written to the destination.

Are there any non-superscaler amd64 cpu (that anyone cares about)?

If the cpu can execute multiple instructions in one clock
then it is usually possible to get the loop control (almost) free.

You might need to unroll once to interleave read/write
but any more may be pointless.
So something like:
	a = *src++
	do {
		b = *src++;
		*dst++ = a;
		a = *src++;
		*dst++ = b;
	} while (src != lim);
	*dst++ = b;

    David

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