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Message-ID: <BYAPR02MB5559D4117C9096D70C5FFE76A5639@BYAPR02MB5559.namprd02.prod.outlook.com>
Date: Wed, 24 Mar 2021 12:35:58 +0000
From: Bharat Kumar Gogada <bharatku@...inx.com>
To: Marc Zyngier <maz@...nel.org>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>
CC: Frank Wunderlich <frank-w@...lic-files.de>,
Thierry Reding <treding@...dia.com>,
Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh@...nel.org>, Will Deacon <will@...nel.org>,
"K. Y. Srinivasan" <kys@...rosoft.com>,
Haiyang Zhang <haiyangz@...rosoft.com>,
Stephen Hemminger <sthemmin@...rosoft.com>,
Michael Kelley <mikelley@...rosoft.com>,
Wei Liu <wei.liu@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Ryder Lee <ryder.lee@...iatek.com>,
Marek Vasut <marek.vasut+renesas@...il.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
Michal Simek <michals@...inx.com>,
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"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
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Subject: RE: [PATCH v2 04/15] PCI: xilinx: Don't allocate extra memory for the
MSI capture address
Thanks Marc for the patch.
> Subject: [PATCH v2 04/15] PCI: xilinx: Don't allocate extra memory for the
> MSI capture address
>
> A long cargo-culted behaviour of PCI drivers is to allocate memory to obtain
> an address that is fed to the controller as the MSI capture address (i.e. the
> MSI doorbell).
>
> But there is no actual requirement for this address to be RAM.
> All it needs to be is a suitable aligned address that will
> *not* be DMA'd to.
>
> Use the physical address of the 'port' data structure as the MSI capture
> address.
>
> Signed-off-by: Marc Zyngier <maz@...nel.org>
> ---
> drivers/pci/controller/pcie-xilinx.c | 18 ++++++------------
> 1 file changed, 6 insertions(+), 12 deletions(-)
...
> - msg.address_hi = 0;
> - msg.address_lo = msg_addr;
> + msg.address_hi = upper_32_bits(msg_addr);
> + msg.address_lo = lower_32_bits(msg_addr);
The XILINX_PCIE_REG_MSIBASE2 register expects 4KB aligned address.
The lower 12-bits are always set to 0 in this register. So we need to mask the address
while programming address to EP.
#define XILINX_PCIE_MSI_ADDR_MASK GENMASK(31, 12)
msg.address_lo = lower_32_bits(msg_addr) & XILINX_PCIE_MSI_ADDR_MASK;
> msg.data = irq;
>
Regards,
Bharat
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