lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <878s6ck8xf.wl-maz@kernel.org>
Date:   Wed, 24 Mar 2021 12:55:40 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     Bharat Kumar Gogada <bharatku@...inx.com>
Cc:     "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Frank Wunderlich <frank-w@...lic-files.de>,
        Thierry Reding <treding@...dia.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Rob Herring <robh@...nel.org>, Will Deacon <will@...nel.org>,
        "K. Y. Srinivasan" <kys@...rosoft.com>,
        Haiyang Zhang <haiyangz@...rosoft.com>,
        Stephen Hemminger <sthemmin@...rosoft.com>,
        Michael Kelley <mikelley@...rosoft.com>,
        Wei Liu <wei.liu@...nel.org>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Ryder Lee <ryder.lee@...iatek.com>,
        Marek Vasut <marek.vasut+renesas@...il.com>,
        Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
        Michal Simek <michals@...inx.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-hyperv@...r.kernel.org" <linux-hyperv@...r.kernel.org>,
        "linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>,
        "kernel-team@...roid.com" <kernel-team@...roid.com>
Subject: Re: [PATCH v2 04/15] PCI: xilinx: Don't allocate extra memory for the MSI capture address

On Wed, 24 Mar 2021 12:35:58 +0000,
Bharat Kumar Gogada <bharatku@...inx.com> wrote:
> 
> Thanks Marc for the patch.
> > Subject: [PATCH v2 04/15] PCI: xilinx: Don't allocate extra memory for the
> > MSI capture address
> > 
> > A long cargo-culted behaviour of PCI drivers is to allocate memory to obtain
> > an address that is fed to the controller as the MSI capture address (i.e. the
> > MSI doorbell).
> > 
> > But there is no actual requirement for this address to be RAM.
> > All it needs to be is a suitable aligned address that will
> > *not* be DMA'd to.
> > 
> > Use the physical address of the 'port' data structure as the MSI capture
> > address.
> > 
> > Signed-off-by: Marc Zyngier <maz@...nel.org>
> > ---
> >  drivers/pci/controller/pcie-xilinx.c | 18 ++++++------------
> >  1 file changed, 6 insertions(+), 12 deletions(-)
> 
> ...
> > -	msg.address_hi = 0;
> > -	msg.address_lo = msg_addr;
> > +	msg.address_hi = upper_32_bits(msg_addr);
> > +	msg.address_lo = lower_32_bits(msg_addr);
> 
> The XILINX_PCIE_REG_MSIBASE2 register expects 4KB aligned address.
> The lower 12-bits are always set to 0 in this register. So we need
> to mask the address while programming address to

Thanks for the heads up, I'll fix this up. Does it work correctly once
the address is aligned?

	M.

-- 
Without deviation from the norm, progress is not possible.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ