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Message-ID: <8cac7848-3a8e-c597-1efc-c67fb6daba25@denx.de>
Date: Wed, 24 Mar 2021 14:21:50 +0100
From: Claudius Heine <ch@...x.de>
To: Jagan Teki <jagan@...rulasolutions.com>,
Rob Herring <robh+dt@...nel.org>,
Andrzej Hajda <a.hajda@...sung.com>,
Neil Armstrong <narmstrong@...libre.com>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...l.net>,
Sam Ravnborg <sam@...nborg.org>
Cc: Marek Vasut <marex@...x.de>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-amarula@...rulasolutions.com
Subject: Re: [PATCH v3 2/2] drm: bridge: Add TI SN65DSI83/84/85 DSI to LVDS
bridge
Hi Jagan,
On 2021-02-14 18:44, Jagan Teki wrote:
[...]
> +static void sn65dsi_enable(struct drm_bridge *bridge)
> +{
> + struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
> + struct drm_display_mode *mode = bridge_to_mode(bridge);
> + int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format);
> + unsigned int lanes = sn->dsi->lanes;
> + unsigned int pixel_clk = mode->clock * 1000;
> + unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2);
> + unsigned int val;
> +
> + /* reset SOFT_RESET bit */
> + regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
> +
> + msleep(10);
> +
> + /* reset PLL_EN bit */
> + regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
> +
> + msleep(10);
> +
> + /* setup lvds clock */
> + val = sn65dsi_get_clk_range(0, 5, pixel_clk, 25000000, 25000000);
> + if (val < 0) {
val is unsigned int, so it can never be negative so this condition is
always false. Same error further down in that function as well.
regards,
Claudius
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