linux-kernel - RE: [PATCH v4 3/3] pinctrl: Add Xilinx ZynqMP pinctrl driver support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <SN6PR02MB39173864459C1AFC0590E5DEBD629@SN6PR02MB3917.namprd02.prod.outlook.com>
Date:   Thu, 25 Mar 2021 10:15:30 +0000
From:   Sai Krishna Potthuri <lakshmis@...inx.com>
To:     Linus Walleij <linus.walleij@...aro.org>
CC:     Andy Shevchenko <andy.shevchenko@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Michal Simek <michals@...inx.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        git <git@...inx.com>,
        "saikrishna12468@...il.com" <saikrishna12468@...il.com>
Subject: RE: [PATCH v4 3/3] pinctrl: Add Xilinx ZynqMP pinctrl driver support

Hi Linus,

> -----Original Message-----
> From: Linus Walleij <linus.walleij@...aro.org>
> Sent: Thursday, March 25, 2021 2:27 PM
> To: Sai Krishna Potthuri <lakshmis@...inx.com>
> Cc: Andy Shevchenko <andy.shevchenko@...il.com>; Rob Herring
> <robh+dt@...nel.org>; Michal Simek <michals@...inx.com>; Greg Kroah-
> Hartman <gregkh@...uxfoundation.org>; linux-arm Mailing List <linux-arm-
> kernel@...ts.infradead.org>; Linux Kernel Mailing List <linux-
> kernel@...r.kernel.org>; devicetree <devicetree@...r.kernel.org>; open
> list:GPIO SUBSYSTEM <linux-gpio@...r.kernel.org>; git <git@...inx.com>;
> saikrishna12468@...il.com
> Subject: Re: [PATCH v4 3/3] pinctrl: Add Xilinx ZynqMP pinctrl driver support
> 
> On Mon, Mar 22, 2021 at 4:25 PM Sai Krishna Potthuri
> <lakshmis@...inx.com> wrote:
> > [Andy]
> 
> > > > > > +       PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1, };
> > > > >
> > > > > I'm lost here. What is IO standard exactly? Why it can't be in
> > > > > generic headers?
> > > > It represents LVCMOS 3.3 volts/ LVCMOS 1.8 volts.
> > > > Since this is specific to Xilinx ZynqMP platform, considered to be
> > > > added in the driver file.
> > >
> > > So, why can't we create a couple of bits to represent this voltages
> > > in the generic header and gain usability for others as well?
> >
> > I see some drivers are maintaining the configuration list in the
> > driver file, if the configuration is specific to the driver.
> >
> > We can move this to generic header if it is used by others as well.
> > Ok, will wait for Linus to comment.
> > >
> > > Linus?
> 
> While it is fine to add custom pin config options to pin controllers for
> hopelessly idiomatic stuff, this does look like it should be using
> PIN_CONFIG_POWER_SOURCE with the voltage rail as parameter, see
> include/linux/pinctrl/pinconf-generic.h
Thanks.
I will update the driver to use 'power-source' option.

Regards
Sai Krishna
> 
> If you're not using that then tell us why.
> 
> Yours,
> Linus Walleij