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Message-ID: <CAJF2gTRiG+5f7y5HXe9EhfDWc3Q+pTEW_8sSFc0iGkbuMJO+NA@mail.gmail.com>
Date: Thu, 25 Mar 2021 19:52:55 +0800
From: Guo Ren <guoren@...nel.org>
To: kernel test robot <lkp@...el.com>
Cc: Anup Patel <Anup.Patel@....com>, kbuild-all@...ts.01.org,
linux-riscv <linux-riscv@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-csky@...r.kernel.org,
linux-arch <linux-arch@...r.kernel.org>,
tech-unixplatformspec@...ts.riscv.org,
Michael Clark <michaeljclark@....com>,
Peter Zijlstra <peterz@...radead.org>,
Anup Patel <anup@...infault.org>
Subject: Re: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 5ca41152cf4b..894e170c503e 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -17,6 +17,14 @@
#define __local_release_fence()
\
__asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory")
+#ifdef CONFIG_32BIT
+#define __ASM_SLLIW "slli\t"
+#define __ASM_SRLIW "srli\t"
+#else
+#define __ASM_SLLIW "slliw\t"
+#define __ASM_SRLIW "srliw\t"
+#endif
+
#define __xchg_relaxed(ptr, new, size) \
({ \
__typeof__(ptr) __ptr = (ptr); \
@@ -31,14 +39,14 @@
__asm__ __volatile__ ( \
"0: lr.w %0, (%4) \n" \
" mv %1, %0 \n" \
- " slliw %1, %1, 16 \n" \
- " srliw %1, %1, 16 \n" \
+ __ASM_SLLIW "%1, %1, 16 \n" \
+ __ASM_SRLIW "%1, %1, 16 \n" \
" mv %2, %3 \n" \
- " slliw %2, %2, 16 \n" \
+ __ASM_SLLIW "%2, %2, 16 \n" \
" or %1, %2, %1 \n" \
" sc.w %2, %1, (%4) \n" \
" bnez %2, 0b \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SRLIW "%0, %0, 16 \n" \
: "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
: "r" (__new), "r"(addr) \
: "memory"); \
@@ -46,14 +54,14 @@
__asm__ __volatile__ ( \
"0: lr.w %0, (%4) \n" \
" mv %1, %0 \n" \
- " srliw %1, %1, 16 \n" \
- " slliw %1, %1, 16 \n" \
+ __ASM_SRLIW "%1, %1, 16 \n" \
+ __ASM_SLLIW "%1, %1, 16 \n" \
" mv %2, %3 \n" \
" or %1, %2, %1 \n" \
" sc.w %2, %1, 0(%4) \n" \
" bnez %2, 0b \n" \
- " slliw %0, %0, 16 \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SLLIW "%0, %0, 16 \n" \
+ __ASM_SRLIW "%0, %0, 16 \n" \
: "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
: "r" (__new), "r"(addr) \
: "memory"); \
On Thu, Mar 25, 2021 at 7:34 PM Guo Ren <guoren@...nel.org> wrote:
>
> haha, I forgot RV32, it needs a
>
> #ifdef RV32
> srliw
> #else
> srli
> #endif
>
> On Thu, Mar 25, 2021 at 7:16 PM kernel test robot <lkp@...el.com> wrote:
> >
> > Hi,
> >
> > Thank you for the patch! Yet something to improve:
> >
> > [auto build test ERROR on tip/locking/core]
> > [also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use '--base' as documented in
> > https://git-scm.com/docs/git-format-patch]
> >
> > url: https://github.com/0day-ci/linux/commits/guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 5965a7adbd72dd9b288c0911cb73719fed1efa08
> > config: riscv-rv32_defconfig (attached as .config)
> > compiler: riscv32-linux-gcc (GCC) 9.3.0
> > reproduce (this is a W=1 build):
> > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > # https://github.com/0day-ci/linux/commit/2bf2d117ab34b007089e20e1c46eff89b5da097e
> > git remote add linux-review https://github.com/0day-ci/linux
> > git fetch --no-tags linux-review guoren-kernel-org/riscv-Add-qspinlock-qrwlock/20210325-155933
> > git checkout 2bf2d117ab34b007089e20e1c46eff89b5da097e
> > # save the attached .config to linux build tree
> > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kernel test robot <lkp@...el.com>
> >
> > All errors (new ones prefixed by >>):
> >
> > kernel/locking/qspinlock.c: Assembler messages:
> > kernel/locking/qspinlock.c:184: Error: unrecognized opcode `srliw t1,t1,16'
> > kernel/locking/qspinlock.c:185: Error: unrecognized opcode `slliw t1,t1,16'
> > >> kernel/locking/qspinlock.c:190: Error: unrecognized opcode `slliw a6,a6,16'
> > >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
> > kernel/locking/qspinlock.c:184: Error: unrecognized opcode `slliw t1,t1,16'
> > kernel/locking/qspinlock.c:185: Error: unrecognized opcode `srliw t1,t1,16'
> > kernel/locking/qspinlock.c:187: Error: unrecognized opcode `slliw t3,t3,16'
> > >> kernel/locking/qspinlock.c:191: Error: unrecognized opcode `srliw a6,a6,16'
> >
> >
> > vim +190 kernel/locking/qspinlock.c
> >
> > 69f9cae90907e0 Peter Zijlstra (Intel 2015-04-24 187)
> > 59fb586b4a07b4 Will Deacon 2018-04-26 188 /**
> > 59fb586b4a07b4 Will Deacon 2018-04-26 189 * clear_pending - clear the pending bit.
> > 59fb586b4a07b4 Will Deacon 2018-04-26 @190 * @lock: Pointer to queued spinlock structure
> > 59fb586b4a07b4 Will Deacon 2018-04-26 @191 *
> > 59fb586b4a07b4 Will Deacon 2018-04-26 192 * *,1,* -> *,0,*
> > 59fb586b4a07b4 Will Deacon 2018-04-26 193 */
> > 59fb586b4a07b4 Will Deacon 2018-04-26 194 static __always_inline void clear_pending(struct qspinlock *lock)
> > 59fb586b4a07b4 Will Deacon 2018-04-26 195 {
> > 59fb586b4a07b4 Will Deacon 2018-04-26 196 atomic_andnot(_Q_PENDING_VAL, &lock->val);
> > 59fb586b4a07b4 Will Deacon 2018-04-26 197 }
> > 59fb586b4a07b4 Will Deacon 2018-04-26 198
> >
> > ---
> > 0-DAY CI Kernel Test Service, Intel Corporation
> > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
>
>
>
> --
> Best Regards
> Guo Ren
>
> ML: https://lore.kernel.org/linux-csky/
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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