| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <1616785332-165261-3-git-send-email-kan.liang@linux.intel.com>
Date: Fri, 26 Mar 2021 12:01:49 -0700
From: kan.liang@...ux.intel.com
To: peterz@...radead.org, mingo@...nel.org,
linux-kernel@...r.kernel.org
Cc: acme@...nel.org, tglx@...utronix.de, bp@...en8.de,
namhyung@...nel.org, jolsa@...hat.com, ak@...ux.intel.com,
yao.jin@...ux.intel.com, alexander.shishkin@...ux.intel.com,
adrian.hunter@...el.com,
Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>,
Andy Lutomirski <luto@...nel.org>,
Dave Hansen <dave.hansen@...el.com>,
Kan Liang <kan.liang@...ux.intel.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
"Ravi V. Shankar" <ravi.v.shankar@...el.com>,
Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
Subject: [PATCH V3 02/25] x86/cpu: Add helper function to get the type of the current hybrid CPU
From: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
On processors with Intel Hybrid Technology (i.e., one having more than
one type of CPU in the same package), all CPUs support the same
instruction set and enumerate the same features on CPUID. Thus, all
software can run on any CPU without restrictions. However, there may be
model-specific differences among types of CPUs. For instance, each type
of CPU may support a different number of performance counters. Also,
machine check error banks may be wired differently. Even though most
software will not care about these differences, kernel subsystems
dealing with these differences must know.
Add and expose a new helper function get_this_hybrid_cpu_type() to query
the type of the current hybrid CPU. The function will be used later in
the perf subsystem.
The Intel Software Developer's Manual defines the CPU type as 8-bit
identifier.
Cc: Andi Kleen <ak@...ux.intel.com>
Cc: Andy Lutomirski <luto@...nel.org>
Cc: Dave Hansen <dave.hansen@...el.com>
Cc: Kan Liang <kan.liang@...ux.intel.com>
Cc: "Peter Zijlstra (Intel)" <peterz@...radead.org>
Cc: "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>
Cc: "Ravi V. Shankar" <ravi.v.shankar@...el.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
Cc: linux-kernel@...r.kernel.org
Reviewed-by: Len Brown <len.brown@...el.com>
Reviewed-by: Tony Luck <tony.luck@...el.com>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
---
Changes since v2 (as part of patchset for perf change for Alderlake)
* Use get_this_hybrid_cpu_type() to replace get_hybrid_cpu_type() to
avoid the trouble of IPIs. The new function retrieves the type of the
current hybrid CPU. It's good enough for perf. (Dave)
* Remove definitions for Atom and Core CPU types. Perf will define a
enum for the hybrid CPU type in the perf_event.h (Peter)
* Remove X86_HYBRID_CPU_NATIVE_MODEL_ID_MASK. Not used in the patch
set. (Kan)
* Update the description accordingly. (Boris)
Changes since v1 (as part of patchset for perf change for Alderlake)
* Removed cpuinfo_x86.x86_cpu_type. It can be added later if needed.
Instead, implement helper functions that subsystems can use.(Boris)
* Add definitions for Atom and Core CPU types. (Kan)
Changes since v1 (in a separate posting)
* Simplify code by using cpuid_eax(). (Boris)
* Reworded the commit message to clarify the concept of Intel Hybrid
Technology. Stress that all CPUs can run the same instruction set
and support the same features.
---
arch/x86/include/asm/cpu.h | 6 ++++++
arch/x86/include/asm/processor.h | 2 ++
arch/x86/kernel/cpu/intel.c | 14 ++++++++++++++
3 files changed, 22 insertions(+)
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index da78ccbd493b..610905d7e541 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -45,6 +45,7 @@ extern void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c);
extern void switch_to_sld(unsigned long tifn);
extern bool handle_user_split_lock(struct pt_regs *regs, long error_code);
extern bool handle_guest_split_lock(unsigned long ip);
+u8 get_this_hybrid_cpu_type(void);
#else
static inline void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) {}
static inline void switch_to_sld(unsigned long tifn) {}
@@ -57,6 +58,11 @@ static inline bool handle_guest_split_lock(unsigned long ip)
{
return false;
}
+
+static inline u8 get_this_hybrid_cpu_type(void)
+{
+ return 0;
+}
#endif
#ifdef CONFIG_IA32_FEAT_CTL
void init_ia32_feat_ctl(struct cpuinfo_x86 *c);
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index dc6d149bf851..746512a68b30 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -166,6 +166,8 @@ enum cpuid_regs_idx {
#define X86_VENDOR_UNKNOWN 0xff
+#define X86_HYBRID_CPU_TYPE_ID_SHIFT 24
+
/*
* capabilities of CPUs
*/
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 0e422a544835..189fcbe16590 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -1195,3 +1195,17 @@ void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c)
cpu_model_supports_sld = true;
split_lock_setup();
}
+
+/**
+ * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
+ *
+ * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in
+ * a hybrid processor. If the processor is not hybrid, returns 0.
+ */
+u8 get_this_hybrid_cpu_type(void)
+{
+ if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
+ return 0;
+
+ return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;
+}
--
2.17.1
Powered by blists - more mailing lists